1 /* 2 * r8a7778 processor support 3 * 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; version 2 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19 */ 20 21 #include <linux/kernel.h> 22 #include <linux/io.h> 23 #include <linux/irqchip/arm-gic.h> 24 #include <linux/of.h> 25 #include <linux/of_platform.h> 26 #include <linux/platform_device.h> 27 #include <linux/irqchip.h> 28 #include <linux/serial_sci.h> 29 #include <linux/sh_timer.h> 30 #include <mach/irqs.h> 31 #include <mach/r8a7778.h> 32 #include <mach/common.h> 33 #include <asm/mach/arch.h> 34 #include <asm/hardware/cache-l2x0.h> 35 36 /* SCIF */ 37 #define SCIF_INFO(baseaddr, irq) \ 38 { \ 39 .mapbase = baseaddr, \ 40 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 41 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ 42 .scbrr_algo_id = SCBRR_ALGO_2, \ 43 .type = PORT_SCIF, \ 44 .irqs = SCIx_IRQ_MUXED(irq), \ 45 } 46 47 static struct plat_sci_port scif_platform_data[] = { 48 SCIF_INFO(0xffe40000, gic_iid(0x66)), 49 SCIF_INFO(0xffe41000, gic_iid(0x67)), 50 SCIF_INFO(0xffe42000, gic_iid(0x68)), 51 SCIF_INFO(0xffe43000, gic_iid(0x69)), 52 SCIF_INFO(0xffe44000, gic_iid(0x6a)), 53 SCIF_INFO(0xffe45000, gic_iid(0x6b)), 54 }; 55 56 /* TMU */ 57 static struct resource sh_tmu0_resources[] = { 58 DEFINE_RES_MEM(0xffd80008, 12), 59 DEFINE_RES_IRQ(gic_iid(0x40)), 60 }; 61 62 static struct sh_timer_config sh_tmu0_platform_data = { 63 .name = "TMU00", 64 .channel_offset = 0x4, 65 .timer_bit = 0, 66 .clockevent_rating = 200, 67 }; 68 69 static struct resource sh_tmu1_resources[] = { 70 DEFINE_RES_MEM(0xffd80014, 12), 71 DEFINE_RES_IRQ(gic_iid(0x41)), 72 }; 73 74 static struct sh_timer_config sh_tmu1_platform_data = { 75 .name = "TMU01", 76 .channel_offset = 0x10, 77 .timer_bit = 1, 78 .clocksource_rating = 200, 79 }; 80 81 #define PLATFORM_INFO(n, i) \ 82 { \ 83 .parent = &platform_bus, \ 84 .name = #n, \ 85 .id = i, \ 86 .res = n ## i ## _resources, \ 87 .num_res = ARRAY_SIZE(n ## i ##_resources), \ 88 .data = &n ## i ##_platform_data, \ 89 .size_data = sizeof(n ## i ## _platform_data), \ 90 } 91 92 struct platform_device_info platform_devinfo[] = { 93 PLATFORM_INFO(sh_tmu, 0), 94 PLATFORM_INFO(sh_tmu, 1), 95 }; 96 97 void __init r8a7778_add_standard_devices(void) 98 { 99 int i; 100 101 #ifdef CONFIG_CACHE_L2X0 102 void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); 103 if (base) { 104 /* 105 * Early BRESP enable, Shared attribute override enable, 64K*16way 106 * don't call iounmap(base) 107 */ 108 l2x0_init(base, 0x40470000, 0x82000fff); 109 } 110 #endif 111 112 for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++) 113 platform_device_register_data(&platform_bus, "sh-sci", i, 114 &scif_platform_data[i], 115 sizeof(struct plat_sci_port)); 116 117 for (i = 0; i < ARRAY_SIZE(platform_devinfo); i++) 118 platform_device_register_full(&platform_devinfo[i]); 119 } 120 121 #define INT2SMSKCR0 0x82288 /* 0xfe782288 */ 122 #define INT2SMSKCR1 0x8228c /* 0xfe78228c */ 123 124 #define INT2NTSR0 0x00018 /* 0xfe700018 */ 125 #define INT2NTSR1 0x0002c /* 0xfe70002c */ 126 static void __init r8a7778_init_irq_common(void) 127 { 128 void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000); 129 130 BUG_ON(!base); 131 132 /* route all interrupts to ARM */ 133 __raw_writel(0x73ffffff, base + INT2NTSR0); 134 __raw_writel(0xffffffff, base + INT2NTSR1); 135 136 /* unmask all known interrupts in INTCS2 */ 137 __raw_writel(0x08330773, base + INT2SMSKCR0); 138 __raw_writel(0x00311110, base + INT2SMSKCR1); 139 140 iounmap(base); 141 } 142 143 void __init r8a7778_init_irq(void) 144 { 145 void __iomem *gic_dist_base; 146 void __iomem *gic_cpu_base; 147 148 gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE); 149 gic_cpu_base = ioremap_nocache(0xfe430000, PAGE_SIZE); 150 BUG_ON(!gic_dist_base || !gic_cpu_base); 151 152 /* use GIC to handle interrupts */ 153 gic_init(0, 29, gic_dist_base, gic_cpu_base); 154 155 r8a7778_init_irq_common(); 156 } 157 158 void __init r8a7778_init_delay(void) 159 { 160 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ 161 } 162 163 #ifdef CONFIG_USE_OF 164 void __init r8a7778_init_irq_dt(void) 165 { 166 irqchip_init(); 167 r8a7778_init_irq_common(); 168 } 169 170 static const struct of_dev_auxdata r8a7778_auxdata_lookup[] __initconst = { 171 {}, 172 }; 173 174 void __init r8a7778_add_standard_devices_dt(void) 175 { 176 of_platform_populate(NULL, of_default_bus_match_table, 177 r8a7778_auxdata_lookup, NULL); 178 } 179 180 static const char *r8a7778_compat_dt[] __initdata = { 181 "renesas,r8a7778", 182 NULL, 183 }; 184 185 DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") 186 .init_early = r8a7778_init_delay, 187 .init_irq = r8a7778_init_irq_dt, 188 .init_machine = r8a7778_add_standard_devices_dt, 189 .init_time = shmobile_timer_init, 190 .dt_compat = r8a7778_compat_dt, 191 MACHINE_END 192 193 #endif /* CONFIG_USE_OF */ 194