1 /* 2 * r8a7778 processor support 3 * 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 * Copyright (C) 2013 Cogent Embedded, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/io.h> 24 #include <linux/irqchip/arm-gic.h> 25 #include <linux/of.h> 26 #include <linux/of_platform.h> 27 #include <linux/platform_data/irq-renesas-intc-irqpin.h> 28 #include <linux/platform_device.h> 29 #include <linux/irqchip.h> 30 #include <linux/serial_sci.h> 31 #include <linux/sh_timer.h> 32 #include <mach/irqs.h> 33 #include <mach/r8a7778.h> 34 #include <mach/common.h> 35 #include <asm/mach/arch.h> 36 #include <asm/hardware/cache-l2x0.h> 37 38 /* SCIF */ 39 #define SCIF_INFO(baseaddr, irq) \ 40 { \ 41 .mapbase = baseaddr, \ 42 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 43 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ 44 .scbrr_algo_id = SCBRR_ALGO_2, \ 45 .type = PORT_SCIF, \ 46 .irqs = SCIx_IRQ_MUXED(irq), \ 47 } 48 49 static struct plat_sci_port scif_platform_data[] = { 50 SCIF_INFO(0xffe40000, gic_iid(0x66)), 51 SCIF_INFO(0xffe41000, gic_iid(0x67)), 52 SCIF_INFO(0xffe42000, gic_iid(0x68)), 53 SCIF_INFO(0xffe43000, gic_iid(0x69)), 54 SCIF_INFO(0xffe44000, gic_iid(0x6a)), 55 SCIF_INFO(0xffe45000, gic_iid(0x6b)), 56 }; 57 58 /* TMU */ 59 static struct resource sh_tmu0_resources[] = { 60 DEFINE_RES_MEM(0xffd80008, 12), 61 DEFINE_RES_IRQ(gic_iid(0x40)), 62 }; 63 64 static struct sh_timer_config sh_tmu0_platform_data = { 65 .name = "TMU00", 66 .channel_offset = 0x4, 67 .timer_bit = 0, 68 .clockevent_rating = 200, 69 }; 70 71 static struct resource sh_tmu1_resources[] = { 72 DEFINE_RES_MEM(0xffd80014, 12), 73 DEFINE_RES_IRQ(gic_iid(0x41)), 74 }; 75 76 static struct sh_timer_config sh_tmu1_platform_data = { 77 .name = "TMU01", 78 .channel_offset = 0x10, 79 .timer_bit = 1, 80 .clocksource_rating = 200, 81 }; 82 83 #define r8a7778_register_tmu(idx) \ 84 platform_device_register_resndata( \ 85 &platform_bus, "sh_tmu", idx, \ 86 sh_tmu##idx##_resources, \ 87 ARRAY_SIZE(sh_tmu##idx##_resources), \ 88 &sh_tmu##idx##_platform_data, \ 89 sizeof(sh_tmu##idx##_platform_data)) 90 91 /* Ether */ 92 static struct resource ether_resources[] = { 93 DEFINE_RES_MEM(0xfde00000, 0x400), 94 DEFINE_RES_IRQ(gic_iid(0x89)), 95 }; 96 97 void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata) 98 { 99 platform_device_register_resndata(&platform_bus, "sh_eth", -1, 100 ether_resources, 101 ARRAY_SIZE(ether_resources), 102 pdata, sizeof(*pdata)); 103 } 104 105 /* SDHI */ 106 static struct resource sdhi_resources[] = { 107 /* SDHI0 */ 108 DEFINE_RES_MEM(0xFFE4C000, 0x100), 109 DEFINE_RES_IRQ(gic_iid(0x77)), 110 /* SDHI1 */ 111 DEFINE_RES_MEM(0xFFE4D000, 0x100), 112 DEFINE_RES_IRQ(gic_iid(0x78)), 113 /* SDHI2 */ 114 DEFINE_RES_MEM(0xFFE4F000, 0x100), 115 DEFINE_RES_IRQ(gic_iid(0x76)), 116 }; 117 118 void __init r8a7778_sdhi_init(int id, 119 struct sh_mobile_sdhi_info *info) 120 { 121 BUG_ON(id < 0 || id > 2); 122 123 platform_device_register_resndata( 124 &platform_bus, "sh_mobile_sdhi", id, 125 sdhi_resources + (2 * id), 2, 126 info, sizeof(*info)); 127 } 128 129 void __init r8a7778_add_standard_devices(void) 130 { 131 int i; 132 133 #ifdef CONFIG_CACHE_L2X0 134 void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); 135 if (base) { 136 /* 137 * Early BRESP enable, Shared attribute override enable, 64K*16way 138 * don't call iounmap(base) 139 */ 140 l2x0_init(base, 0x40470000, 0x82000fff); 141 } 142 #endif 143 144 for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++) 145 platform_device_register_data(&platform_bus, "sh-sci", i, 146 &scif_platform_data[i], 147 sizeof(struct plat_sci_port)); 148 149 r8a7778_register_tmu(0); 150 r8a7778_register_tmu(1); 151 } 152 153 static struct renesas_intc_irqpin_config irqpin_platform_data = { 154 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ 155 .sense_bitfield_width = 2, 156 }; 157 158 static struct resource irqpin_resources[] = { 159 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ 160 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ 161 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ 162 DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ 163 DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ 164 DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */ 165 DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */ 166 DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */ 167 DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */ 168 }; 169 170 void __init r8a7778_init_irq_extpin(int irlm) 171 { 172 void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); 173 unsigned long tmp; 174 175 if (!icr0) { 176 pr_warn("r8a7778: unable to setup external irq pin mode\n"); 177 return; 178 } 179 180 tmp = ioread32(icr0); 181 if (irlm) 182 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ 183 else 184 tmp &= ~(1 << 23); /* IRL mode - not supported */ 185 tmp |= (1 << 21); /* LVLMODE = 1 */ 186 iowrite32(tmp, icr0); 187 iounmap(icr0); 188 189 if (irlm) 190 platform_device_register_resndata( 191 &platform_bus, "renesas_intc_irqpin", -1, 192 irqpin_resources, ARRAY_SIZE(irqpin_resources), 193 &irqpin_platform_data, sizeof(irqpin_platform_data)); 194 } 195 196 #define INT2SMSKCR0 0x82288 /* 0xfe782288 */ 197 #define INT2SMSKCR1 0x8228c /* 0xfe78228c */ 198 199 #define INT2NTSR0 0x00018 /* 0xfe700018 */ 200 #define INT2NTSR1 0x0002c /* 0xfe70002c */ 201 static void __init r8a7778_init_irq_common(void) 202 { 203 void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000); 204 205 BUG_ON(!base); 206 207 /* route all interrupts to ARM */ 208 __raw_writel(0x73ffffff, base + INT2NTSR0); 209 __raw_writel(0xffffffff, base + INT2NTSR1); 210 211 /* unmask all known interrupts in INTCS2 */ 212 __raw_writel(0x08330773, base + INT2SMSKCR0); 213 __raw_writel(0x00311110, base + INT2SMSKCR1); 214 215 iounmap(base); 216 } 217 218 void __init r8a7778_init_irq(void) 219 { 220 void __iomem *gic_dist_base; 221 void __iomem *gic_cpu_base; 222 223 gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE); 224 gic_cpu_base = ioremap_nocache(0xfe430000, PAGE_SIZE); 225 BUG_ON(!gic_dist_base || !gic_cpu_base); 226 227 /* use GIC to handle interrupts */ 228 gic_init(0, 29, gic_dist_base, gic_cpu_base); 229 230 r8a7778_init_irq_common(); 231 } 232 233 void __init r8a7778_init_delay(void) 234 { 235 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ 236 } 237 238 #ifdef CONFIG_USE_OF 239 void __init r8a7778_init_irq_dt(void) 240 { 241 irqchip_init(); 242 r8a7778_init_irq_common(); 243 } 244 245 static const struct of_dev_auxdata r8a7778_auxdata_lookup[] __initconst = { 246 {}, 247 }; 248 249 void __init r8a7778_add_standard_devices_dt(void) 250 { 251 of_platform_populate(NULL, of_default_bus_match_table, 252 r8a7778_auxdata_lookup, NULL); 253 } 254 255 static const char *r8a7778_compat_dt[] __initdata = { 256 "renesas,r8a7778", 257 NULL, 258 }; 259 260 DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") 261 .init_early = r8a7778_init_delay, 262 .init_irq = r8a7778_init_irq_dt, 263 .init_machine = r8a7778_add_standard_devices_dt, 264 .init_time = shmobile_timer_init, 265 .dt_compat = r8a7778_compat_dt, 266 MACHINE_END 267 268 #endif /* CONFIG_USE_OF */ 269