1 /* 2 * r8a7778 processor support 3 * 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; version 2 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19 */ 20 21 #include <linux/kernel.h> 22 #include <linux/io.h> 23 #include <linux/irqchip/arm-gic.h> 24 #include <linux/of.h> 25 #include <linux/of_platform.h> 26 #include <linux/platform_device.h> 27 #include <linux/irqchip.h> 28 #include <linux/serial_sci.h> 29 #include <linux/sh_timer.h> 30 #include <mach/irqs.h> 31 #include <mach/r8a7778.h> 32 #include <mach/common.h> 33 #include <asm/mach/arch.h> 34 #include <asm/hardware/cache-l2x0.h> 35 36 /* SCIF */ 37 #define SCIF_INFO(baseaddr, irq) \ 38 { \ 39 .mapbase = baseaddr, \ 40 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 41 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ 42 .scbrr_algo_id = SCBRR_ALGO_2, \ 43 .type = PORT_SCIF, \ 44 .irqs = SCIx_IRQ_MUXED(irq), \ 45 } 46 47 static struct plat_sci_port scif_platform_data[] = { 48 SCIF_INFO(0xffe40000, gic_iid(0x66)), 49 SCIF_INFO(0xffe41000, gic_iid(0x67)), 50 SCIF_INFO(0xffe42000, gic_iid(0x68)), 51 SCIF_INFO(0xffe43000, gic_iid(0x69)), 52 SCIF_INFO(0xffe44000, gic_iid(0x6a)), 53 SCIF_INFO(0xffe45000, gic_iid(0x6b)), 54 }; 55 56 /* TMU */ 57 static struct resource sh_tmu0_resources[] = { 58 DEFINE_RES_MEM(0xffd80008, 12), 59 DEFINE_RES_IRQ(gic_iid(0x40)), 60 }; 61 62 static struct sh_timer_config sh_tmu0_platform_data = { 63 .name = "TMU00", 64 .channel_offset = 0x4, 65 .timer_bit = 0, 66 .clockevent_rating = 200, 67 }; 68 69 static struct resource sh_tmu1_resources[] = { 70 DEFINE_RES_MEM(0xffd80014, 12), 71 DEFINE_RES_IRQ(gic_iid(0x41)), 72 }; 73 74 static struct sh_timer_config sh_tmu1_platform_data = { 75 .name = "TMU01", 76 .channel_offset = 0x10, 77 .timer_bit = 1, 78 .clocksource_rating = 200, 79 }; 80 81 #define r8a7778_register_tmu(idx) \ 82 platform_device_register_resndata( \ 83 &platform_bus, "sh_tmu", idx, \ 84 sh_tmu##idx##_resources, \ 85 ARRAY_SIZE(sh_tmu##idx##_resources), \ 86 &sh_tmu##idx##_platform_data, \ 87 sizeof(sh_tmu##idx##_platform_data)) 88 89 void __init r8a7778_add_standard_devices(void) 90 { 91 int i; 92 93 #ifdef CONFIG_CACHE_L2X0 94 void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); 95 if (base) { 96 /* 97 * Early BRESP enable, Shared attribute override enable, 64K*16way 98 * don't call iounmap(base) 99 */ 100 l2x0_init(base, 0x40470000, 0x82000fff); 101 } 102 #endif 103 104 for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++) 105 platform_device_register_data(&platform_bus, "sh-sci", i, 106 &scif_platform_data[i], 107 sizeof(struct plat_sci_port)); 108 109 r8a7778_register_tmu(0); 110 r8a7778_register_tmu(1); 111 } 112 113 #define INT2SMSKCR0 0x82288 /* 0xfe782288 */ 114 #define INT2SMSKCR1 0x8228c /* 0xfe78228c */ 115 116 #define INT2NTSR0 0x00018 /* 0xfe700018 */ 117 #define INT2NTSR1 0x0002c /* 0xfe70002c */ 118 static void __init r8a7778_init_irq_common(void) 119 { 120 void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000); 121 122 BUG_ON(!base); 123 124 /* route all interrupts to ARM */ 125 __raw_writel(0x73ffffff, base + INT2NTSR0); 126 __raw_writel(0xffffffff, base + INT2NTSR1); 127 128 /* unmask all known interrupts in INTCS2 */ 129 __raw_writel(0x08330773, base + INT2SMSKCR0); 130 __raw_writel(0x00311110, base + INT2SMSKCR1); 131 132 iounmap(base); 133 } 134 135 void __init r8a7778_init_irq(void) 136 { 137 void __iomem *gic_dist_base; 138 void __iomem *gic_cpu_base; 139 140 gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE); 141 gic_cpu_base = ioremap_nocache(0xfe430000, PAGE_SIZE); 142 BUG_ON(!gic_dist_base || !gic_cpu_base); 143 144 /* use GIC to handle interrupts */ 145 gic_init(0, 29, gic_dist_base, gic_cpu_base); 146 147 r8a7778_init_irq_common(); 148 } 149 150 void __init r8a7778_init_delay(void) 151 { 152 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ 153 } 154 155 #ifdef CONFIG_USE_OF 156 void __init r8a7778_init_irq_dt(void) 157 { 158 irqchip_init(); 159 r8a7778_init_irq_common(); 160 } 161 162 static const struct of_dev_auxdata r8a7778_auxdata_lookup[] __initconst = { 163 {}, 164 }; 165 166 void __init r8a7778_add_standard_devices_dt(void) 167 { 168 of_platform_populate(NULL, of_default_bus_match_table, 169 r8a7778_auxdata_lookup, NULL); 170 } 171 172 static const char *r8a7778_compat_dt[] __initdata = { 173 "renesas,r8a7778", 174 NULL, 175 }; 176 177 DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") 178 .init_early = r8a7778_init_delay, 179 .init_irq = r8a7778_init_irq_dt, 180 .init_machine = r8a7778_add_standard_devices_dt, 181 .init_time = shmobile_timer_init, 182 .dt_compat = r8a7778_compat_dt, 183 MACHINE_END 184 185 #endif /* CONFIG_USE_OF */ 186