1 /* 2 * r8a7778 processor support 3 * 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; version 2 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19 */ 20 21 #include <linux/kernel.h> 22 #include <linux/io.h> 23 #include <linux/irqchip/arm-gic.h> 24 #include <linux/of.h> 25 #include <linux/of_platform.h> 26 #include <linux/platform_data/irq-renesas-intc-irqpin.h> 27 #include <linux/platform_device.h> 28 #include <linux/irqchip.h> 29 #include <linux/serial_sci.h> 30 #include <linux/sh_timer.h> 31 #include <mach/irqs.h> 32 #include <mach/r8a7778.h> 33 #include <mach/common.h> 34 #include <asm/mach/arch.h> 35 #include <asm/hardware/cache-l2x0.h> 36 37 /* SCIF */ 38 #define SCIF_INFO(baseaddr, irq) \ 39 { \ 40 .mapbase = baseaddr, \ 41 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 42 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ 43 .scbrr_algo_id = SCBRR_ALGO_2, \ 44 .type = PORT_SCIF, \ 45 .irqs = SCIx_IRQ_MUXED(irq), \ 46 } 47 48 static struct plat_sci_port scif_platform_data[] = { 49 SCIF_INFO(0xffe40000, gic_iid(0x66)), 50 SCIF_INFO(0xffe41000, gic_iid(0x67)), 51 SCIF_INFO(0xffe42000, gic_iid(0x68)), 52 SCIF_INFO(0xffe43000, gic_iid(0x69)), 53 SCIF_INFO(0xffe44000, gic_iid(0x6a)), 54 SCIF_INFO(0xffe45000, gic_iid(0x6b)), 55 }; 56 57 /* TMU */ 58 static struct resource sh_tmu0_resources[] = { 59 DEFINE_RES_MEM(0xffd80008, 12), 60 DEFINE_RES_IRQ(gic_iid(0x40)), 61 }; 62 63 static struct sh_timer_config sh_tmu0_platform_data = { 64 .name = "TMU00", 65 .channel_offset = 0x4, 66 .timer_bit = 0, 67 .clockevent_rating = 200, 68 }; 69 70 static struct resource sh_tmu1_resources[] = { 71 DEFINE_RES_MEM(0xffd80014, 12), 72 DEFINE_RES_IRQ(gic_iid(0x41)), 73 }; 74 75 static struct sh_timer_config sh_tmu1_platform_data = { 76 .name = "TMU01", 77 .channel_offset = 0x10, 78 .timer_bit = 1, 79 .clocksource_rating = 200, 80 }; 81 82 #define r8a7778_register_tmu(idx) \ 83 platform_device_register_resndata( \ 84 &platform_bus, "sh_tmu", idx, \ 85 sh_tmu##idx##_resources, \ 86 ARRAY_SIZE(sh_tmu##idx##_resources), \ 87 &sh_tmu##idx##_platform_data, \ 88 sizeof(sh_tmu##idx##_platform_data)) 89 90 void __init r8a7778_add_standard_devices(void) 91 { 92 int i; 93 94 #ifdef CONFIG_CACHE_L2X0 95 void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); 96 if (base) { 97 /* 98 * Early BRESP enable, Shared attribute override enable, 64K*16way 99 * don't call iounmap(base) 100 */ 101 l2x0_init(base, 0x40470000, 0x82000fff); 102 } 103 #endif 104 105 for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++) 106 platform_device_register_data(&platform_bus, "sh-sci", i, 107 &scif_platform_data[i], 108 sizeof(struct plat_sci_port)); 109 110 r8a7778_register_tmu(0); 111 r8a7778_register_tmu(1); 112 } 113 114 static struct renesas_intc_irqpin_config irqpin_platform_data = { 115 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ 116 .sense_bitfield_width = 2, 117 }; 118 119 static struct resource irqpin_resources[] = { 120 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ 121 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ 122 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ 123 DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ 124 DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ 125 DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */ 126 DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */ 127 DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */ 128 DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */ 129 }; 130 131 void __init r8a7778_init_irq_extpin(int irlm) 132 { 133 void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); 134 unsigned long tmp; 135 136 if (!icr0) { 137 pr_warn("r8a7778: unable to setup external irq pin mode\n"); 138 return; 139 } 140 141 tmp = ioread32(icr0); 142 if (irlm) 143 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ 144 else 145 tmp &= ~(1 << 23); /* IRL mode - not supported */ 146 tmp |= (1 << 21); /* LVLMODE = 1 */ 147 iowrite32(tmp, icr0); 148 iounmap(icr0); 149 150 if (irlm) 151 platform_device_register_resndata( 152 &platform_bus, "renesas_intc_irqpin", -1, 153 irqpin_resources, ARRAY_SIZE(irqpin_resources), 154 &irqpin_platform_data, sizeof(irqpin_platform_data)); 155 } 156 157 #define INT2SMSKCR0 0x82288 /* 0xfe782288 */ 158 #define INT2SMSKCR1 0x8228c /* 0xfe78228c */ 159 160 #define INT2NTSR0 0x00018 /* 0xfe700018 */ 161 #define INT2NTSR1 0x0002c /* 0xfe70002c */ 162 static void __init r8a7778_init_irq_common(void) 163 { 164 void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000); 165 166 BUG_ON(!base); 167 168 /* route all interrupts to ARM */ 169 __raw_writel(0x73ffffff, base + INT2NTSR0); 170 __raw_writel(0xffffffff, base + INT2NTSR1); 171 172 /* unmask all known interrupts in INTCS2 */ 173 __raw_writel(0x08330773, base + INT2SMSKCR0); 174 __raw_writel(0x00311110, base + INT2SMSKCR1); 175 176 iounmap(base); 177 } 178 179 void __init r8a7778_init_irq(void) 180 { 181 void __iomem *gic_dist_base; 182 void __iomem *gic_cpu_base; 183 184 gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE); 185 gic_cpu_base = ioremap_nocache(0xfe430000, PAGE_SIZE); 186 BUG_ON(!gic_dist_base || !gic_cpu_base); 187 188 /* use GIC to handle interrupts */ 189 gic_init(0, 29, gic_dist_base, gic_cpu_base); 190 191 r8a7778_init_irq_common(); 192 } 193 194 void __init r8a7778_init_delay(void) 195 { 196 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ 197 } 198 199 #ifdef CONFIG_USE_OF 200 void __init r8a7778_init_irq_dt(void) 201 { 202 irqchip_init(); 203 r8a7778_init_irq_common(); 204 } 205 206 static const struct of_dev_auxdata r8a7778_auxdata_lookup[] __initconst = { 207 {}, 208 }; 209 210 void __init r8a7778_add_standard_devices_dt(void) 211 { 212 of_platform_populate(NULL, of_default_bus_match_table, 213 r8a7778_auxdata_lookup, NULL); 214 } 215 216 static const char *r8a7778_compat_dt[] __initdata = { 217 "renesas,r8a7778", 218 NULL, 219 }; 220 221 DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") 222 .init_early = r8a7778_init_delay, 223 .init_irq = r8a7778_init_irq_dt, 224 .init_machine = r8a7778_add_standard_devices_dt, 225 .init_time = shmobile_timer_init, 226 .dt_compat = r8a7778_compat_dt, 227 MACHINE_END 228 229 #endif /* CONFIG_USE_OF */ 230