1 /* 2 * r8a7778 processor support 3 * 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 * Copyright (C) 2013 Cogent Embedded, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/io.h> 24 #include <linux/irqchip/arm-gic.h> 25 #include <linux/of.h> 26 #include <linux/of_platform.h> 27 #include <linux/platform_data/gpio-rcar.h> 28 #include <linux/platform_data/irq-renesas-intc-irqpin.h> 29 #include <linux/platform_device.h> 30 #include <linux/irqchip.h> 31 #include <linux/serial_sci.h> 32 #include <linux/sh_timer.h> 33 #include <mach/irqs.h> 34 #include <mach/r8a7778.h> 35 #include <mach/common.h> 36 #include <asm/mach/arch.h> 37 #include <asm/hardware/cache-l2x0.h> 38 39 /* SCIF */ 40 #define SCIF_INFO(baseaddr, irq) \ 41 { \ 42 .mapbase = baseaddr, \ 43 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 44 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ 45 .scbrr_algo_id = SCBRR_ALGO_2, \ 46 .type = PORT_SCIF, \ 47 .irqs = SCIx_IRQ_MUXED(irq), \ 48 } 49 50 static struct plat_sci_port scif_platform_data[] = { 51 SCIF_INFO(0xffe40000, gic_iid(0x66)), 52 SCIF_INFO(0xffe41000, gic_iid(0x67)), 53 SCIF_INFO(0xffe42000, gic_iid(0x68)), 54 SCIF_INFO(0xffe43000, gic_iid(0x69)), 55 SCIF_INFO(0xffe44000, gic_iid(0x6a)), 56 SCIF_INFO(0xffe45000, gic_iid(0x6b)), 57 }; 58 59 /* TMU */ 60 static struct resource sh_tmu0_resources[] = { 61 DEFINE_RES_MEM(0xffd80008, 12), 62 DEFINE_RES_IRQ(gic_iid(0x40)), 63 }; 64 65 static struct sh_timer_config sh_tmu0_platform_data = { 66 .name = "TMU00", 67 .channel_offset = 0x4, 68 .timer_bit = 0, 69 .clockevent_rating = 200, 70 }; 71 72 static struct resource sh_tmu1_resources[] = { 73 DEFINE_RES_MEM(0xffd80014, 12), 74 DEFINE_RES_IRQ(gic_iid(0x41)), 75 }; 76 77 static struct sh_timer_config sh_tmu1_platform_data = { 78 .name = "TMU01", 79 .channel_offset = 0x10, 80 .timer_bit = 1, 81 .clocksource_rating = 200, 82 }; 83 84 /* Ether */ 85 static struct resource ether_resources[] = { 86 DEFINE_RES_MEM(0xfde00000, 0x400), 87 DEFINE_RES_IRQ(gic_iid(0x89)), 88 }; 89 90 #define r8a7778_register_tmu(idx) \ 91 platform_device_register_resndata( \ 92 &platform_bus, "sh_tmu", idx, \ 93 sh_tmu##idx##_resources, \ 94 ARRAY_SIZE(sh_tmu##idx##_resources), \ 95 &sh_tmu##idx##_platform_data, \ 96 sizeof(sh_tmu##idx##_platform_data)) 97 98 /* PFC/GPIO */ 99 static struct resource pfc_resources[] = { 100 DEFINE_RES_MEM(0xfffc0000, 0x118), 101 }; 102 103 #define R8A7778_GPIO(idx) \ 104 static struct resource r8a7778_gpio##idx##_resources[] = { \ 105 DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30), \ 106 DEFINE_RES_IRQ(gic_iid(0x87)), \ 107 }; \ 108 \ 109 static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data = { \ 110 .gpio_base = 32 * (idx), \ 111 .irq_base = GPIO_IRQ_BASE(idx), \ 112 .number_of_pins = 32, \ 113 .pctl_name = "pfc-r8a7778", \ 114 } 115 116 R8A7778_GPIO(0); 117 R8A7778_GPIO(1); 118 R8A7778_GPIO(2); 119 R8A7778_GPIO(3); 120 R8A7778_GPIO(4); 121 122 #define r8a7778_register_gpio(idx) \ 123 platform_device_register_resndata( \ 124 &platform_bus, "gpio_rcar", idx, \ 125 r8a7778_gpio##idx##_resources, \ 126 ARRAY_SIZE(r8a7778_gpio##idx##_resources), \ 127 &r8a7778_gpio##idx##_platform_data, \ 128 sizeof(r8a7778_gpio##idx##_platform_data)) 129 130 void __init r8a7778_pinmux_init(void) 131 { 132 platform_device_register_simple( 133 "pfc-r8a7778", -1, 134 pfc_resources, 135 ARRAY_SIZE(pfc_resources)); 136 137 r8a7778_register_gpio(0); 138 r8a7778_register_gpio(1); 139 r8a7778_register_gpio(2); 140 r8a7778_register_gpio(3); 141 r8a7778_register_gpio(4); 142 } 143 144 void __init r8a7778_add_standard_devices(void) 145 { 146 int i; 147 148 #ifdef CONFIG_CACHE_L2X0 149 void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); 150 if (base) { 151 /* 152 * Early BRESP enable, Shared attribute override enable, 64K*16way 153 * don't call iounmap(base) 154 */ 155 l2x0_init(base, 0x40470000, 0x82000fff); 156 } 157 #endif 158 159 for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++) 160 platform_device_register_data(&platform_bus, "sh-sci", i, 161 &scif_platform_data[i], 162 sizeof(struct plat_sci_port)); 163 164 r8a7778_register_tmu(0); 165 r8a7778_register_tmu(1); 166 } 167 168 void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata) 169 { 170 platform_device_register_resndata(&platform_bus, "sh_eth", -1, 171 ether_resources, 172 ARRAY_SIZE(ether_resources), 173 pdata, sizeof(*pdata)); 174 } 175 176 static struct renesas_intc_irqpin_config irqpin_platform_data = { 177 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ 178 .sense_bitfield_width = 2, 179 }; 180 181 static struct resource irqpin_resources[] = { 182 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ 183 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ 184 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ 185 DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ 186 DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ 187 DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */ 188 DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */ 189 DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */ 190 DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */ 191 }; 192 193 void __init r8a7778_init_irq_extpin(int irlm) 194 { 195 void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); 196 unsigned long tmp; 197 198 if (!icr0) { 199 pr_warn("r8a7778: unable to setup external irq pin mode\n"); 200 return; 201 } 202 203 tmp = ioread32(icr0); 204 if (irlm) 205 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ 206 else 207 tmp &= ~(1 << 23); /* IRL mode - not supported */ 208 tmp |= (1 << 21); /* LVLMODE = 1 */ 209 iowrite32(tmp, icr0); 210 iounmap(icr0); 211 212 if (irlm) 213 platform_device_register_resndata( 214 &platform_bus, "renesas_intc_irqpin", -1, 215 irqpin_resources, ARRAY_SIZE(irqpin_resources), 216 &irqpin_platform_data, sizeof(irqpin_platform_data)); 217 } 218 219 #define INT2SMSKCR0 0x82288 /* 0xfe782288 */ 220 #define INT2SMSKCR1 0x8228c /* 0xfe78228c */ 221 222 #define INT2NTSR0 0x00018 /* 0xfe700018 */ 223 #define INT2NTSR1 0x0002c /* 0xfe70002c */ 224 static void __init r8a7778_init_irq_common(void) 225 { 226 void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000); 227 228 BUG_ON(!base); 229 230 /* route all interrupts to ARM */ 231 __raw_writel(0x73ffffff, base + INT2NTSR0); 232 __raw_writel(0xffffffff, base + INT2NTSR1); 233 234 /* unmask all known interrupts in INTCS2 */ 235 __raw_writel(0x08330773, base + INT2SMSKCR0); 236 __raw_writel(0x00311110, base + INT2SMSKCR1); 237 238 iounmap(base); 239 } 240 241 void __init r8a7778_init_irq(void) 242 { 243 void __iomem *gic_dist_base; 244 void __iomem *gic_cpu_base; 245 246 gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE); 247 gic_cpu_base = ioremap_nocache(0xfe430000, PAGE_SIZE); 248 BUG_ON(!gic_dist_base || !gic_cpu_base); 249 250 /* use GIC to handle interrupts */ 251 gic_init(0, 29, gic_dist_base, gic_cpu_base); 252 253 r8a7778_init_irq_common(); 254 } 255 256 void __init r8a7778_init_delay(void) 257 { 258 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ 259 } 260 261 #ifdef CONFIG_USE_OF 262 void __init r8a7778_init_irq_dt(void) 263 { 264 irqchip_init(); 265 r8a7778_init_irq_common(); 266 } 267 268 static const struct of_dev_auxdata r8a7778_auxdata_lookup[] __initconst = { 269 {}, 270 }; 271 272 void __init r8a7778_add_standard_devices_dt(void) 273 { 274 of_platform_populate(NULL, of_default_bus_match_table, 275 r8a7778_auxdata_lookup, NULL); 276 } 277 278 static const char *r8a7778_compat_dt[] __initdata = { 279 "renesas,r8a7778", 280 NULL, 281 }; 282 283 DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") 284 .init_early = r8a7778_init_delay, 285 .init_irq = r8a7778_init_irq_dt, 286 .init_machine = r8a7778_add_standard_devices_dt, 287 .init_time = shmobile_timer_init, 288 .dt_compat = r8a7778_compat_dt, 289 MACHINE_END 290 291 #endif /* CONFIG_USE_OF */ 292