1 /* 2 * r8a7778 processor support 3 * 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 * Copyright (C) 2013 Cogent Embedded, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/io.h> 24 #include <linux/irqchip/arm-gic.h> 25 #include <linux/of.h> 26 #include <linux/of_platform.h> 27 #include <linux/platform_data/dma-rcar-hpbdma.h> 28 #include <linux/platform_data/gpio-rcar.h> 29 #include <linux/platform_data/irq-renesas-intc-irqpin.h> 30 #include <linux/platform_device.h> 31 #include <linux/irqchip.h> 32 #include <linux/serial_sci.h> 33 #include <linux/sh_timer.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/usb/phy.h> 36 #include <linux/usb/hcd.h> 37 #include <linux/usb/ehci_pdriver.h> 38 #include <linux/usb/ohci_pdriver.h> 39 #include <linux/dma-mapping.h> 40 #include <mach/irqs.h> 41 #include <mach/r8a7778.h> 42 #include <mach/common.h> 43 #include <asm/mach/arch.h> 44 #include <asm/hardware/cache-l2x0.h> 45 46 /* SCIF */ 47 #define SCIF_INFO(baseaddr, irq) \ 48 { \ 49 .mapbase = baseaddr, \ 50 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 51 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ 52 .scbrr_algo_id = SCBRR_ALGO_2, \ 53 .type = PORT_SCIF, \ 54 .irqs = SCIx_IRQ_MUXED(irq), \ 55 } 56 57 static struct plat_sci_port scif_platform_data[] __initdata = { 58 SCIF_INFO(0xffe40000, gic_iid(0x66)), 59 SCIF_INFO(0xffe41000, gic_iid(0x67)), 60 SCIF_INFO(0xffe42000, gic_iid(0x68)), 61 SCIF_INFO(0xffe43000, gic_iid(0x69)), 62 SCIF_INFO(0xffe44000, gic_iid(0x6a)), 63 SCIF_INFO(0xffe45000, gic_iid(0x6b)), 64 }; 65 66 /* TMU */ 67 static struct resource sh_tmu0_resources[] __initdata = { 68 DEFINE_RES_MEM(0xffd80008, 12), 69 DEFINE_RES_IRQ(gic_iid(0x40)), 70 }; 71 72 static struct sh_timer_config sh_tmu0_platform_data __initdata = { 73 .name = "TMU00", 74 .channel_offset = 0x4, 75 .timer_bit = 0, 76 .clockevent_rating = 200, 77 }; 78 79 static struct resource sh_tmu1_resources[] __initdata = { 80 DEFINE_RES_MEM(0xffd80014, 12), 81 DEFINE_RES_IRQ(gic_iid(0x41)), 82 }; 83 84 static struct sh_timer_config sh_tmu1_platform_data __initdata = { 85 .name = "TMU01", 86 .channel_offset = 0x10, 87 .timer_bit = 1, 88 .clocksource_rating = 200, 89 }; 90 91 #define r8a7778_register_tmu(idx) \ 92 platform_device_register_resndata( \ 93 &platform_bus, "sh_tmu", idx, \ 94 sh_tmu##idx##_resources, \ 95 ARRAY_SIZE(sh_tmu##idx##_resources), \ 96 &sh_tmu##idx##_platform_data, \ 97 sizeof(sh_tmu##idx##_platform_data)) 98 99 int r8a7778_usb_phy_power(bool enable) 100 { 101 static struct usb_phy *phy = NULL; 102 int ret = 0; 103 104 if (!phy) 105 phy = usb_get_phy(USB_PHY_TYPE_USB2); 106 107 if (IS_ERR(phy)) { 108 pr_err("kernel doesn't have usb phy driver\n"); 109 return PTR_ERR(phy); 110 } 111 112 if (enable) 113 ret = usb_phy_init(phy); 114 else 115 usb_phy_shutdown(phy); 116 117 return ret; 118 } 119 120 /* USB */ 121 static int usb_power_on(struct platform_device *pdev) 122 { 123 int ret = r8a7778_usb_phy_power(true); 124 125 if (ret) 126 return ret; 127 128 pm_runtime_enable(&pdev->dev); 129 pm_runtime_get_sync(&pdev->dev); 130 131 return 0; 132 } 133 134 static void usb_power_off(struct platform_device *pdev) 135 { 136 if (r8a7778_usb_phy_power(false)) 137 return; 138 139 pm_runtime_put_sync(&pdev->dev); 140 pm_runtime_disable(&pdev->dev); 141 } 142 143 static int ehci_init_internal_buffer(struct usb_hcd *hcd) 144 { 145 /* 146 * Below are recommended values from the datasheet; 147 * see [USB :: Setting of EHCI Internal Buffer]. 148 */ 149 /* EHCI IP internal buffer setting */ 150 iowrite32(0x00ff0040, hcd->regs + 0x0094); 151 /* EHCI IP internal buffer enable */ 152 iowrite32(0x00000001, hcd->regs + 0x009C); 153 154 return 0; 155 } 156 157 static struct usb_ehci_pdata ehci_pdata __initdata = { 158 .power_on = usb_power_on, 159 .power_off = usb_power_off, 160 .power_suspend = usb_power_off, 161 .pre_setup = ehci_init_internal_buffer, 162 }; 163 164 static struct resource ehci_resources[] __initdata = { 165 DEFINE_RES_MEM(0xffe70000, 0x400), 166 DEFINE_RES_IRQ(gic_iid(0x4c)), 167 }; 168 169 static struct usb_ohci_pdata ohci_pdata __initdata = { 170 .power_on = usb_power_on, 171 .power_off = usb_power_off, 172 .power_suspend = usb_power_off, 173 }; 174 175 static struct resource ohci_resources[] __initdata = { 176 DEFINE_RES_MEM(0xffe70400, 0x400), 177 DEFINE_RES_IRQ(gic_iid(0x4c)), 178 }; 179 180 #define USB_PLATFORM_INFO(hci) \ 181 static struct platform_device_info hci##_info __initdata = { \ 182 .parent = &platform_bus, \ 183 .name = #hci "-platform", \ 184 .id = -1, \ 185 .res = hci##_resources, \ 186 .num_res = ARRAY_SIZE(hci##_resources), \ 187 .data = &hci##_pdata, \ 188 .size_data = sizeof(hci##_pdata), \ 189 .dma_mask = DMA_BIT_MASK(32), \ 190 } 191 192 USB_PLATFORM_INFO(ehci); 193 USB_PLATFORM_INFO(ohci); 194 195 /* Ether */ 196 static struct resource ether_resources[] __initdata = { 197 DEFINE_RES_MEM(0xfde00000, 0x400), 198 DEFINE_RES_IRQ(gic_iid(0x89)), 199 }; 200 201 void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata) 202 { 203 platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1, 204 ether_resources, 205 ARRAY_SIZE(ether_resources), 206 pdata, sizeof(*pdata)); 207 } 208 209 /* PFC/GPIO */ 210 static struct resource pfc_resources[] __initdata = { 211 DEFINE_RES_MEM(0xfffc0000, 0x118), 212 }; 213 214 #define R8A7778_GPIO(idx) \ 215 static struct resource r8a7778_gpio##idx##_resources[] __initdata = { \ 216 DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30), \ 217 DEFINE_RES_IRQ(gic_iid(0x87)), \ 218 }; \ 219 \ 220 static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data __initdata = { \ 221 .gpio_base = 32 * (idx), \ 222 .irq_base = GPIO_IRQ_BASE(idx), \ 223 .number_of_pins = 32, \ 224 .pctl_name = "pfc-r8a7778", \ 225 } 226 227 R8A7778_GPIO(0); 228 R8A7778_GPIO(1); 229 R8A7778_GPIO(2); 230 R8A7778_GPIO(3); 231 R8A7778_GPIO(4); 232 233 #define r8a7778_register_gpio(idx) \ 234 platform_device_register_resndata( \ 235 &platform_bus, "gpio_rcar", idx, \ 236 r8a7778_gpio##idx##_resources, \ 237 ARRAY_SIZE(r8a7778_gpio##idx##_resources), \ 238 &r8a7778_gpio##idx##_platform_data, \ 239 sizeof(r8a7778_gpio##idx##_platform_data)) 240 241 void __init r8a7778_pinmux_init(void) 242 { 243 platform_device_register_simple( 244 "pfc-r8a7778", -1, 245 pfc_resources, 246 ARRAY_SIZE(pfc_resources)); 247 248 r8a7778_register_gpio(0); 249 r8a7778_register_gpio(1); 250 r8a7778_register_gpio(2); 251 r8a7778_register_gpio(3); 252 r8a7778_register_gpio(4); 253 }; 254 255 /* I2C */ 256 static struct resource i2c_resources[] __initdata = { 257 /* I2C0 */ 258 DEFINE_RES_MEM(0xffc70000, 0x1000), 259 DEFINE_RES_IRQ(gic_iid(0x63)), 260 /* I2C1 */ 261 DEFINE_RES_MEM(0xffc71000, 0x1000), 262 DEFINE_RES_IRQ(gic_iid(0x6e)), 263 /* I2C2 */ 264 DEFINE_RES_MEM(0xffc72000, 0x1000), 265 DEFINE_RES_IRQ(gic_iid(0x6c)), 266 /* I2C3 */ 267 DEFINE_RES_MEM(0xffc73000, 0x1000), 268 DEFINE_RES_IRQ(gic_iid(0x6d)), 269 }; 270 271 static void __init r8a7778_register_i2c(int id) 272 { 273 BUG_ON(id < 0 || id > 3); 274 275 platform_device_register_simple( 276 "i2c-rcar", id, 277 i2c_resources + (2 * id), 2); 278 } 279 280 /* HSPI */ 281 static struct resource hspi_resources[] __initdata = { 282 /* HSPI0 */ 283 DEFINE_RES_MEM(0xfffc7000, 0x18), 284 DEFINE_RES_IRQ(gic_iid(0x5f)), 285 /* HSPI1 */ 286 DEFINE_RES_MEM(0xfffc8000, 0x18), 287 DEFINE_RES_IRQ(gic_iid(0x74)), 288 /* HSPI2 */ 289 DEFINE_RES_MEM(0xfffc6000, 0x18), 290 DEFINE_RES_IRQ(gic_iid(0x75)), 291 }; 292 293 void __init r8a7778_register_hspi(int id) 294 { 295 BUG_ON(id < 0 || id > 2); 296 297 platform_device_register_simple( 298 "sh-hspi", id, 299 hspi_resources + (2 * id), 2); 300 } 301 302 /* VIN */ 303 #define R8A7778_VIN(idx) \ 304 static struct resource vin##idx##_resources[] __initdata = { \ 305 DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000), \ 306 DEFINE_RES_IRQ(gic_iid(0x5a)), \ 307 }; \ 308 \ 309 static struct platform_device_info vin##idx##_info __initdata = { \ 310 .parent = &platform_bus, \ 311 .name = "r8a7778-vin", \ 312 .id = idx, \ 313 .res = vin##idx##_resources, \ 314 .num_res = ARRAY_SIZE(vin##idx##_resources), \ 315 .dma_mask = DMA_BIT_MASK(32), \ 316 } 317 318 R8A7778_VIN(0); 319 R8A7778_VIN(1); 320 321 static struct platform_device_info *vin_info_table[] __initdata = { 322 &vin0_info, 323 &vin1_info, 324 }; 325 326 void __init r8a7778_add_vin_device(int id, struct rcar_vin_platform_data *pdata) 327 { 328 BUG_ON(id < 0 || id > 1); 329 330 vin_info_table[id]->data = pdata; 331 vin_info_table[id]->size_data = sizeof(*pdata); 332 333 platform_device_register_full(vin_info_table[id]); 334 } 335 336 void __init r8a7778_add_dt_devices(void) 337 { 338 int i; 339 340 #ifdef CONFIG_CACHE_L2X0 341 void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); 342 if (base) { 343 /* 344 * Early BRESP enable, Shared attribute override enable, 64K*16way 345 * don't call iounmap(base) 346 */ 347 l2x0_init(base, 0x40470000, 0x82000fff); 348 } 349 #endif 350 351 for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++) 352 platform_device_register_data(&platform_bus, "sh-sci", i, 353 &scif_platform_data[i], 354 sizeof(struct plat_sci_port)); 355 356 r8a7778_register_tmu(0); 357 r8a7778_register_tmu(1); 358 } 359 360 /* HPB-DMA */ 361 362 /* Asynchronous mode register (ASYNCMDR) bits */ 363 #define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(2) /* SDHI0 */ 364 #define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(2) /* SDHI0 */ 365 #define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */ 366 #define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(1) /* SDHI0 */ 367 #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1) /* SDHI0 */ 368 #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */ 369 370 static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = { 371 { 372 .id = HPBDMA_SLAVE_SDHI0_TX, 373 .addr = 0xffe4c000 + 0x30, 374 .dcr = HPB_DMAE_DCR_SPDS_16BIT | 375 HPB_DMAE_DCR_DMDL | 376 HPB_DMAE_DCR_DPDS_16BIT, 377 .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | 378 HPB_DMAE_ASYNCRSTR_ASRST22 | 379 HPB_DMAE_ASYNCRSTR_ASRST23, 380 .mdr = HPB_DMAE_ASYNCMDR_ASMD21_MULTI, 381 .mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK, 382 .port = 0x0D0C, 383 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, 384 .dma_ch = 21, 385 }, { 386 .id = HPBDMA_SLAVE_SDHI0_RX, 387 .addr = 0xffe4c000 + 0x30, 388 .dcr = HPB_DMAE_DCR_SMDL | 389 HPB_DMAE_DCR_SPDS_16BIT | 390 HPB_DMAE_DCR_DPDS_16BIT, 391 .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | 392 HPB_DMAE_ASYNCRSTR_ASRST22 | 393 HPB_DMAE_ASYNCRSTR_ASRST23, 394 .mdr = HPB_DMAE_ASYNCMDR_ASMD22_MULTI, 395 .mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK, 396 .port = 0x0D0C, 397 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, 398 .dma_ch = 22, 399 }, 400 }; 401 402 static const struct hpb_dmae_channel hpb_dmae_channels[] = { 403 HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */ 404 HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */ 405 }; 406 407 static struct hpb_dmae_pdata dma_platform_data __initdata = { 408 .slaves = hpb_dmae_slaves, 409 .num_slaves = ARRAY_SIZE(hpb_dmae_slaves), 410 .channels = hpb_dmae_channels, 411 .num_channels = ARRAY_SIZE(hpb_dmae_channels), 412 .ts_shift = { 413 [XMIT_SZ_8BIT] = 0, 414 [XMIT_SZ_16BIT] = 1, 415 [XMIT_SZ_32BIT] = 2, 416 }, 417 .num_hw_channels = 39, 418 }; 419 420 static struct resource hpb_dmae_resources[] __initdata = { 421 /* Channel registers */ 422 DEFINE_RES_MEM(0xffc08000, 0x1000), 423 /* Common registers */ 424 DEFINE_RES_MEM(0xffc09000, 0x170), 425 /* Asynchronous reset registers */ 426 DEFINE_RES_MEM(0xffc00300, 4), 427 /* Asynchronous mode registers */ 428 DEFINE_RES_MEM(0xffc00400, 4), 429 /* IRQ for DMA channels */ 430 DEFINE_RES_NAMED(gic_iid(0x7b), 5, NULL, IORESOURCE_IRQ), 431 }; 432 433 static void __init r8a7778_register_hpb_dmae(void) 434 { 435 platform_device_register_resndata(&platform_bus, "hpb-dma-engine", -1, 436 hpb_dmae_resources, 437 ARRAY_SIZE(hpb_dmae_resources), 438 &dma_platform_data, 439 sizeof(dma_platform_data)); 440 } 441 442 void __init r8a7778_add_standard_devices(void) 443 { 444 r8a7778_add_dt_devices(); 445 r8a7778_register_i2c(0); 446 r8a7778_register_i2c(1); 447 r8a7778_register_i2c(2); 448 r8a7778_register_i2c(3); 449 r8a7778_register_hspi(0); 450 r8a7778_register_hspi(1); 451 r8a7778_register_hspi(2); 452 453 r8a7778_register_hpb_dmae(); 454 } 455 456 void __init r8a7778_init_late(void) 457 { 458 platform_device_register_full(&ehci_info); 459 platform_device_register_full(&ohci_info); 460 } 461 462 static struct renesas_intc_irqpin_config irqpin_platform_data __initdata = { 463 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ 464 .sense_bitfield_width = 2, 465 }; 466 467 static struct resource irqpin_resources[] __initdata = { 468 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ 469 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ 470 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ 471 DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ 472 DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ 473 DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */ 474 DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */ 475 DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */ 476 DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */ 477 }; 478 479 void __init r8a7778_init_irq_extpin(int irlm) 480 { 481 void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); 482 unsigned long tmp; 483 484 if (!icr0) { 485 pr_warn("r8a7778: unable to setup external irq pin mode\n"); 486 return; 487 } 488 489 tmp = ioread32(icr0); 490 if (irlm) 491 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ 492 else 493 tmp &= ~(1 << 23); /* IRL mode - not supported */ 494 tmp |= (1 << 21); /* LVLMODE = 1 */ 495 iowrite32(tmp, icr0); 496 iounmap(icr0); 497 498 if (irlm) 499 platform_device_register_resndata( 500 &platform_bus, "renesas_intc_irqpin", -1, 501 irqpin_resources, ARRAY_SIZE(irqpin_resources), 502 &irqpin_platform_data, sizeof(irqpin_platform_data)); 503 } 504 505 void __init r8a7778_init_delay(void) 506 { 507 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ 508 } 509 510 #ifdef CONFIG_USE_OF 511 #define INT2SMSKCR0 0x82288 /* 0xfe782288 */ 512 #define INT2SMSKCR1 0x8228c /* 0xfe78228c */ 513 514 #define INT2NTSR0 0x00018 /* 0xfe700018 */ 515 #define INT2NTSR1 0x0002c /* 0xfe70002c */ 516 void __init r8a7778_init_irq_dt(void) 517 { 518 void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000); 519 520 BUG_ON(!base); 521 522 irqchip_init(); 523 524 /* route all interrupts to ARM */ 525 __raw_writel(0x73ffffff, base + INT2NTSR0); 526 __raw_writel(0xffffffff, base + INT2NTSR1); 527 528 /* unmask all known interrupts in INTCS2 */ 529 __raw_writel(0x08330773, base + INT2SMSKCR0); 530 __raw_writel(0x00311110, base + INT2SMSKCR1); 531 532 iounmap(base); 533 } 534 535 static const char *r8a7778_compat_dt[] __initdata = { 536 "renesas,r8a7778", 537 NULL, 538 }; 539 540 DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") 541 .init_early = r8a7778_init_delay, 542 .init_irq = r8a7778_init_irq_dt, 543 .dt_compat = r8a7778_compat_dt, 544 .init_late = r8a7778_init_late, 545 MACHINE_END 546 547 #endif /* CONFIG_USE_OF */ 548