1 /* 2 * r8a7778 processor support 3 * 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 * Copyright (C) 2013 Cogent Embedded, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/io.h> 24 #include <linux/irqchip/arm-gic.h> 25 #include <linux/of.h> 26 #include <linux/of_platform.h> 27 #include <linux/platform_data/dma-rcar-hpbdma.h> 28 #include <linux/platform_data/gpio-rcar.h> 29 #include <linux/platform_data/irq-renesas-intc-irqpin.h> 30 #include <linux/platform_device.h> 31 #include <linux/irqchip.h> 32 #include <linux/serial_sci.h> 33 #include <linux/sh_timer.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/usb/phy.h> 36 #include <linux/usb/hcd.h> 37 #include <linux/usb/ehci_pdriver.h> 38 #include <linux/usb/ohci_pdriver.h> 39 #include <linux/dma-mapping.h> 40 #include <mach/irqs.h> 41 #include <mach/r8a7778.h> 42 #include <mach/common.h> 43 #include <asm/mach/arch.h> 44 #include <asm/hardware/cache-l2x0.h> 45 46 /* SCIF */ 47 #define SCIF_INFO(baseaddr, irq) \ 48 { \ 49 .mapbase = baseaddr, \ 50 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 51 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ 52 .scbrr_algo_id = SCBRR_ALGO_2, \ 53 .type = PORT_SCIF, \ 54 .irqs = SCIx_IRQ_MUXED(irq), \ 55 } 56 57 static struct plat_sci_port scif_platform_data[] __initdata = { 58 SCIF_INFO(0xffe40000, gic_iid(0x66)), 59 SCIF_INFO(0xffe41000, gic_iid(0x67)), 60 SCIF_INFO(0xffe42000, gic_iid(0x68)), 61 SCIF_INFO(0xffe43000, gic_iid(0x69)), 62 SCIF_INFO(0xffe44000, gic_iid(0x6a)), 63 SCIF_INFO(0xffe45000, gic_iid(0x6b)), 64 }; 65 66 /* TMU */ 67 static struct resource sh_tmu0_resources[] __initdata = { 68 DEFINE_RES_MEM(0xffd80008, 12), 69 DEFINE_RES_IRQ(gic_iid(0x40)), 70 }; 71 72 static struct sh_timer_config sh_tmu0_platform_data __initdata = { 73 .name = "TMU00", 74 .channel_offset = 0x4, 75 .timer_bit = 0, 76 .clockevent_rating = 200, 77 }; 78 79 static struct resource sh_tmu1_resources[] __initdata = { 80 DEFINE_RES_MEM(0xffd80014, 12), 81 DEFINE_RES_IRQ(gic_iid(0x41)), 82 }; 83 84 static struct sh_timer_config sh_tmu1_platform_data __initdata = { 85 .name = "TMU01", 86 .channel_offset = 0x10, 87 .timer_bit = 1, 88 .clocksource_rating = 200, 89 }; 90 91 #define r8a7778_register_tmu(idx) \ 92 platform_device_register_resndata( \ 93 &platform_bus, "sh_tmu", idx, \ 94 sh_tmu##idx##_resources, \ 95 ARRAY_SIZE(sh_tmu##idx##_resources), \ 96 &sh_tmu##idx##_platform_data, \ 97 sizeof(sh_tmu##idx##_platform_data)) 98 99 int r8a7778_usb_phy_power(bool enable) 100 { 101 static struct usb_phy *phy = NULL; 102 int ret = 0; 103 104 if (!phy) 105 phy = usb_get_phy(USB_PHY_TYPE_USB2); 106 107 if (IS_ERR(phy)) { 108 pr_err("kernel doesn't have usb phy driver\n"); 109 return PTR_ERR(phy); 110 } 111 112 if (enable) 113 ret = usb_phy_init(phy); 114 else 115 usb_phy_shutdown(phy); 116 117 return ret; 118 } 119 120 /* USB */ 121 static int usb_power_on(struct platform_device *pdev) 122 { 123 int ret = r8a7778_usb_phy_power(true); 124 125 if (ret) 126 return ret; 127 128 pm_runtime_enable(&pdev->dev); 129 pm_runtime_get_sync(&pdev->dev); 130 131 return 0; 132 } 133 134 static void usb_power_off(struct platform_device *pdev) 135 { 136 if (r8a7778_usb_phy_power(false)) 137 return; 138 139 pm_runtime_put_sync(&pdev->dev); 140 pm_runtime_disable(&pdev->dev); 141 } 142 143 static int ehci_init_internal_buffer(struct usb_hcd *hcd) 144 { 145 /* 146 * Below are recommended values from the datasheet; 147 * see [USB :: Setting of EHCI Internal Buffer]. 148 */ 149 /* EHCI IP internal buffer setting */ 150 iowrite32(0x00ff0040, hcd->regs + 0x0094); 151 /* EHCI IP internal buffer enable */ 152 iowrite32(0x00000001, hcd->regs + 0x009C); 153 154 return 0; 155 } 156 157 static struct usb_ehci_pdata ehci_pdata __initdata = { 158 .power_on = usb_power_on, 159 .power_off = usb_power_off, 160 .power_suspend = usb_power_off, 161 .pre_setup = ehci_init_internal_buffer, 162 }; 163 164 static struct resource ehci_resources[] __initdata = { 165 DEFINE_RES_MEM(0xffe70000, 0x400), 166 DEFINE_RES_IRQ(gic_iid(0x4c)), 167 }; 168 169 static struct usb_ohci_pdata ohci_pdata __initdata = { 170 .power_on = usb_power_on, 171 .power_off = usb_power_off, 172 .power_suspend = usb_power_off, 173 }; 174 175 static struct resource ohci_resources[] __initdata = { 176 DEFINE_RES_MEM(0xffe70400, 0x400), 177 DEFINE_RES_IRQ(gic_iid(0x4c)), 178 }; 179 180 #define USB_PLATFORM_INFO(hci) \ 181 static struct platform_device_info hci##_info __initdata = { \ 182 .parent = &platform_bus, \ 183 .name = #hci "-platform", \ 184 .id = -1, \ 185 .res = hci##_resources, \ 186 .num_res = ARRAY_SIZE(hci##_resources), \ 187 .data = &hci##_pdata, \ 188 .size_data = sizeof(hci##_pdata), \ 189 .dma_mask = DMA_BIT_MASK(32), \ 190 } 191 192 USB_PLATFORM_INFO(ehci); 193 USB_PLATFORM_INFO(ohci); 194 195 /* PFC/GPIO */ 196 static struct resource pfc_resources[] __initdata = { 197 DEFINE_RES_MEM(0xfffc0000, 0x118), 198 }; 199 200 #define R8A7778_GPIO(idx) \ 201 static struct resource r8a7778_gpio##idx##_resources[] __initdata = { \ 202 DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30), \ 203 DEFINE_RES_IRQ(gic_iid(0x87)), \ 204 }; \ 205 \ 206 static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data __initdata = { \ 207 .gpio_base = 32 * (idx), \ 208 .irq_base = GPIO_IRQ_BASE(idx), \ 209 .number_of_pins = 32, \ 210 .pctl_name = "pfc-r8a7778", \ 211 } 212 213 R8A7778_GPIO(0); 214 R8A7778_GPIO(1); 215 R8A7778_GPIO(2); 216 R8A7778_GPIO(3); 217 R8A7778_GPIO(4); 218 219 #define r8a7778_register_gpio(idx) \ 220 platform_device_register_resndata( \ 221 &platform_bus, "gpio_rcar", idx, \ 222 r8a7778_gpio##idx##_resources, \ 223 ARRAY_SIZE(r8a7778_gpio##idx##_resources), \ 224 &r8a7778_gpio##idx##_platform_data, \ 225 sizeof(r8a7778_gpio##idx##_platform_data)) 226 227 void __init r8a7778_pinmux_init(void) 228 { 229 platform_device_register_simple( 230 "pfc-r8a7778", -1, 231 pfc_resources, 232 ARRAY_SIZE(pfc_resources)); 233 234 r8a7778_register_gpio(0); 235 r8a7778_register_gpio(1); 236 r8a7778_register_gpio(2); 237 r8a7778_register_gpio(3); 238 r8a7778_register_gpio(4); 239 }; 240 241 /* I2C */ 242 static struct resource i2c_resources[] __initdata = { 243 /* I2C0 */ 244 DEFINE_RES_MEM(0xffc70000, 0x1000), 245 DEFINE_RES_IRQ(gic_iid(0x63)), 246 /* I2C1 */ 247 DEFINE_RES_MEM(0xffc71000, 0x1000), 248 DEFINE_RES_IRQ(gic_iid(0x6e)), 249 /* I2C2 */ 250 DEFINE_RES_MEM(0xffc72000, 0x1000), 251 DEFINE_RES_IRQ(gic_iid(0x6c)), 252 /* I2C3 */ 253 DEFINE_RES_MEM(0xffc73000, 0x1000), 254 DEFINE_RES_IRQ(gic_iid(0x6d)), 255 }; 256 257 static void __init r8a7778_register_i2c(int id) 258 { 259 BUG_ON(id < 0 || id > 3); 260 261 platform_device_register_simple( 262 "i2c-rcar", id, 263 i2c_resources + (2 * id), 2); 264 } 265 266 /* HSPI */ 267 static struct resource hspi_resources[] __initdata = { 268 /* HSPI0 */ 269 DEFINE_RES_MEM(0xfffc7000, 0x18), 270 DEFINE_RES_IRQ(gic_iid(0x5f)), 271 /* HSPI1 */ 272 DEFINE_RES_MEM(0xfffc8000, 0x18), 273 DEFINE_RES_IRQ(gic_iid(0x74)), 274 /* HSPI2 */ 275 DEFINE_RES_MEM(0xfffc6000, 0x18), 276 DEFINE_RES_IRQ(gic_iid(0x75)), 277 }; 278 279 static void __init r8a7778_register_hspi(int id) 280 { 281 BUG_ON(id < 0 || id > 2); 282 283 platform_device_register_simple( 284 "sh-hspi", id, 285 hspi_resources + (2 * id), 2); 286 } 287 288 void __init r8a7778_add_dt_devices(void) 289 { 290 int i; 291 292 #ifdef CONFIG_CACHE_L2X0 293 void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); 294 if (base) { 295 /* 296 * Early BRESP enable, Shared attribute override enable, 64K*16way 297 * don't call iounmap(base) 298 */ 299 l2x0_init(base, 0x40470000, 0x82000fff); 300 } 301 #endif 302 303 for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++) 304 platform_device_register_data(&platform_bus, "sh-sci", i, 305 &scif_platform_data[i], 306 sizeof(struct plat_sci_port)); 307 308 r8a7778_register_tmu(0); 309 r8a7778_register_tmu(1); 310 } 311 312 /* HPB-DMA */ 313 314 /* Asynchronous mode register (ASYNCMDR) bits */ 315 #define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(2) /* SDHI0 */ 316 #define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(2) /* SDHI0 */ 317 #define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */ 318 #define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(1) /* SDHI0 */ 319 #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1) /* SDHI0 */ 320 #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */ 321 322 static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = { 323 { 324 .id = HPBDMA_SLAVE_SDHI0_TX, 325 .addr = 0xffe4c000 + 0x30, 326 .dcr = HPB_DMAE_DCR_SPDS_16BIT | 327 HPB_DMAE_DCR_DMDL | 328 HPB_DMAE_DCR_DPDS_16BIT, 329 .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | 330 HPB_DMAE_ASYNCRSTR_ASRST22 | 331 HPB_DMAE_ASYNCRSTR_ASRST23, 332 .mdr = HPB_DMAE_ASYNCMDR_ASMD21_MULTI, 333 .mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK, 334 .port = 0x0D0C, 335 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, 336 .dma_ch = 21, 337 }, { 338 .id = HPBDMA_SLAVE_SDHI0_RX, 339 .addr = 0xffe4c000 + 0x30, 340 .dcr = HPB_DMAE_DCR_SMDL | 341 HPB_DMAE_DCR_SPDS_16BIT | 342 HPB_DMAE_DCR_DPDS_16BIT, 343 .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | 344 HPB_DMAE_ASYNCRSTR_ASRST22 | 345 HPB_DMAE_ASYNCRSTR_ASRST23, 346 .mdr = HPB_DMAE_ASYNCMDR_ASMD22_MULTI, 347 .mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK, 348 .port = 0x0D0C, 349 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, 350 .dma_ch = 22, 351 }, 352 }; 353 354 static const struct hpb_dmae_channel hpb_dmae_channels[] = { 355 HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */ 356 HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */ 357 }; 358 359 static struct hpb_dmae_pdata dma_platform_data __initdata = { 360 .slaves = hpb_dmae_slaves, 361 .num_slaves = ARRAY_SIZE(hpb_dmae_slaves), 362 .channels = hpb_dmae_channels, 363 .num_channels = ARRAY_SIZE(hpb_dmae_channels), 364 .ts_shift = { 365 [XMIT_SZ_8BIT] = 0, 366 [XMIT_SZ_16BIT] = 1, 367 [XMIT_SZ_32BIT] = 2, 368 }, 369 .num_hw_channels = 39, 370 }; 371 372 static struct resource hpb_dmae_resources[] __initdata = { 373 /* Channel registers */ 374 DEFINE_RES_MEM(0xffc08000, 0x1000), 375 /* Common registers */ 376 DEFINE_RES_MEM(0xffc09000, 0x170), 377 /* Asynchronous reset registers */ 378 DEFINE_RES_MEM(0xffc00300, 4), 379 /* Asynchronous mode registers */ 380 DEFINE_RES_MEM(0xffc00400, 4), 381 /* IRQ for DMA channels */ 382 DEFINE_RES_NAMED(gic_iid(0x7b), 5, NULL, IORESOURCE_IRQ), 383 }; 384 385 static void __init r8a7778_register_hpb_dmae(void) 386 { 387 platform_device_register_resndata(&platform_bus, "hpb-dma-engine", -1, 388 hpb_dmae_resources, 389 ARRAY_SIZE(hpb_dmae_resources), 390 &dma_platform_data, 391 sizeof(dma_platform_data)); 392 } 393 394 void __init r8a7778_add_standard_devices(void) 395 { 396 r8a7778_add_dt_devices(); 397 r8a7778_register_i2c(0); 398 r8a7778_register_i2c(1); 399 r8a7778_register_i2c(2); 400 r8a7778_register_i2c(3); 401 r8a7778_register_hspi(0); 402 r8a7778_register_hspi(1); 403 r8a7778_register_hspi(2); 404 405 r8a7778_register_hpb_dmae(); 406 } 407 408 void __init r8a7778_init_late(void) 409 { 410 platform_device_register_full(&ehci_info); 411 platform_device_register_full(&ohci_info); 412 } 413 414 static struct renesas_intc_irqpin_config irqpin_platform_data __initdata = { 415 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ 416 .sense_bitfield_width = 2, 417 }; 418 419 static struct resource irqpin_resources[] __initdata = { 420 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ 421 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ 422 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ 423 DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ 424 DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ 425 DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */ 426 DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */ 427 DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */ 428 DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */ 429 }; 430 431 void __init r8a7778_init_irq_extpin_dt(int irlm) 432 { 433 void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); 434 unsigned long tmp; 435 436 if (!icr0) { 437 pr_warn("r8a7778: unable to setup external irq pin mode\n"); 438 return; 439 } 440 441 tmp = ioread32(icr0); 442 if (irlm) 443 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ 444 else 445 tmp &= ~(1 << 23); /* IRL mode - not supported */ 446 tmp |= (1 << 21); /* LVLMODE = 1 */ 447 iowrite32(tmp, icr0); 448 iounmap(icr0); 449 } 450 451 void __init r8a7778_init_irq_extpin(int irlm) 452 { 453 r8a7778_init_irq_extpin_dt(irlm); 454 if (irlm) 455 platform_device_register_resndata( 456 &platform_bus, "renesas_intc_irqpin", -1, 457 irqpin_resources, ARRAY_SIZE(irqpin_resources), 458 &irqpin_platform_data, sizeof(irqpin_platform_data)); 459 } 460 461 void __init r8a7778_init_delay(void) 462 { 463 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ 464 } 465 466 #ifdef CONFIG_USE_OF 467 #define INT2SMSKCR0 0x82288 /* 0xfe782288 */ 468 #define INT2SMSKCR1 0x8228c /* 0xfe78228c */ 469 470 #define INT2NTSR0 0x00018 /* 0xfe700018 */ 471 #define INT2NTSR1 0x0002c /* 0xfe70002c */ 472 void __init r8a7778_init_irq_dt(void) 473 { 474 void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000); 475 476 BUG_ON(!base); 477 478 irqchip_init(); 479 480 /* route all interrupts to ARM */ 481 __raw_writel(0x73ffffff, base + INT2NTSR0); 482 __raw_writel(0xffffffff, base + INT2NTSR1); 483 484 /* unmask all known interrupts in INTCS2 */ 485 __raw_writel(0x08330773, base + INT2SMSKCR0); 486 __raw_writel(0x00311110, base + INT2SMSKCR1); 487 488 iounmap(base); 489 } 490 491 static const char *r8a7778_compat_dt[] __initdata = { 492 "renesas,r8a7778", 493 NULL, 494 }; 495 496 DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") 497 .init_early = r8a7778_init_delay, 498 .init_irq = r8a7778_init_irq_dt, 499 .dt_compat = r8a7778_compat_dt, 500 .init_late = r8a7778_init_late, 501 MACHINE_END 502 503 #endif /* CONFIG_USE_OF */ 504