1 /* 2 * r8a7778 processor support 3 * 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 * Copyright (C) 2013 Cogent Embedded, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/io.h> 24 #include <linux/irqchip/arm-gic.h> 25 #include <linux/of.h> 26 #include <linux/of_platform.h> 27 #include <linux/platform_data/irq-renesas-intc-irqpin.h> 28 #include <linux/platform_device.h> 29 #include <linux/irqchip.h> 30 #include <linux/serial_sci.h> 31 #include <linux/sh_timer.h> 32 #include <mach/irqs.h> 33 #include <mach/r8a7778.h> 34 #include <mach/common.h> 35 #include <asm/mach/arch.h> 36 #include <asm/hardware/cache-l2x0.h> 37 38 /* SCIF */ 39 #define SCIF_INFO(baseaddr, irq) \ 40 { \ 41 .mapbase = baseaddr, \ 42 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 43 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ 44 .scbrr_algo_id = SCBRR_ALGO_2, \ 45 .type = PORT_SCIF, \ 46 .irqs = SCIx_IRQ_MUXED(irq), \ 47 } 48 49 static struct plat_sci_port scif_platform_data[] = { 50 SCIF_INFO(0xffe40000, gic_iid(0x66)), 51 SCIF_INFO(0xffe41000, gic_iid(0x67)), 52 SCIF_INFO(0xffe42000, gic_iid(0x68)), 53 SCIF_INFO(0xffe43000, gic_iid(0x69)), 54 SCIF_INFO(0xffe44000, gic_iid(0x6a)), 55 SCIF_INFO(0xffe45000, gic_iid(0x6b)), 56 }; 57 58 /* TMU */ 59 static struct resource sh_tmu0_resources[] = { 60 DEFINE_RES_MEM(0xffd80008, 12), 61 DEFINE_RES_IRQ(gic_iid(0x40)), 62 }; 63 64 static struct sh_timer_config sh_tmu0_platform_data = { 65 .name = "TMU00", 66 .channel_offset = 0x4, 67 .timer_bit = 0, 68 .clockevent_rating = 200, 69 }; 70 71 static struct resource sh_tmu1_resources[] = { 72 DEFINE_RES_MEM(0xffd80014, 12), 73 DEFINE_RES_IRQ(gic_iid(0x41)), 74 }; 75 76 static struct sh_timer_config sh_tmu1_platform_data = { 77 .name = "TMU01", 78 .channel_offset = 0x10, 79 .timer_bit = 1, 80 .clocksource_rating = 200, 81 }; 82 83 #define r8a7778_register_tmu(idx) \ 84 platform_device_register_resndata( \ 85 &platform_bus, "sh_tmu", idx, \ 86 sh_tmu##idx##_resources, \ 87 ARRAY_SIZE(sh_tmu##idx##_resources), \ 88 &sh_tmu##idx##_platform_data, \ 89 sizeof(sh_tmu##idx##_platform_data)) 90 91 /* Ether */ 92 static struct resource ether_resources[] = { 93 DEFINE_RES_MEM(0xfde00000, 0x400), 94 DEFINE_RES_IRQ(gic_iid(0x89)), 95 }; 96 97 void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata) 98 { 99 platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1, 100 ether_resources, 101 ARRAY_SIZE(ether_resources), 102 pdata, sizeof(*pdata)); 103 } 104 105 /* SDHI */ 106 static struct resource sdhi_resources[] = { 107 /* SDHI0 */ 108 DEFINE_RES_MEM(0xFFE4C000, 0x100), 109 DEFINE_RES_IRQ(gic_iid(0x77)), 110 /* SDHI1 */ 111 DEFINE_RES_MEM(0xFFE4D000, 0x100), 112 DEFINE_RES_IRQ(gic_iid(0x78)), 113 /* SDHI2 */ 114 DEFINE_RES_MEM(0xFFE4F000, 0x100), 115 DEFINE_RES_IRQ(gic_iid(0x76)), 116 }; 117 118 void __init r8a7778_sdhi_init(int id, 119 struct sh_mobile_sdhi_info *info) 120 { 121 BUG_ON(id < 0 || id > 2); 122 123 platform_device_register_resndata( 124 &platform_bus, "sh_mobile_sdhi", id, 125 sdhi_resources + (2 * id), 2, 126 info, sizeof(*info)); 127 } 128 129 /* I2C */ 130 static struct resource i2c_resources[] __initdata = { 131 /* I2C0 */ 132 DEFINE_RES_MEM(0xffc70000, 0x1000), 133 DEFINE_RES_IRQ(gic_iid(0x63)), 134 /* I2C1 */ 135 DEFINE_RES_MEM(0xffc71000, 0x1000), 136 DEFINE_RES_IRQ(gic_iid(0x6e)), 137 /* I2C2 */ 138 DEFINE_RES_MEM(0xffc72000, 0x1000), 139 DEFINE_RES_IRQ(gic_iid(0x6c)), 140 /* I2C3 */ 141 DEFINE_RES_MEM(0xffc73000, 0x1000), 142 DEFINE_RES_IRQ(gic_iid(0x6d)), 143 }; 144 145 void __init r8a7778_add_i2c_device(int id) 146 { 147 BUG_ON(id < 0 || id > 3); 148 149 platform_device_register_simple( 150 "i2c-rcar", id, 151 i2c_resources + (2 * id), 2); 152 } 153 154 /* HSPI */ 155 static struct resource hspi_resources[] __initdata = { 156 /* HSPI0 */ 157 DEFINE_RES_MEM(0xfffc7000, 0x18), 158 DEFINE_RES_IRQ(gic_iid(0x5f)), 159 /* HSPI1 */ 160 DEFINE_RES_MEM(0xfffc8000, 0x18), 161 DEFINE_RES_IRQ(gic_iid(0x74)), 162 /* HSPI2 */ 163 DEFINE_RES_MEM(0xfffc6000, 0x18), 164 DEFINE_RES_IRQ(gic_iid(0x75)), 165 }; 166 167 void __init r8a7778_add_hspi_device(int id) 168 { 169 BUG_ON(id < 0 || id > 2); 170 171 platform_device_register_simple( 172 "sh-hspi", id, 173 hspi_resources + (2 * id), 2); 174 } 175 176 /* MMC */ 177 static struct resource mmc_resources[] __initdata = { 178 DEFINE_RES_MEM(0xffe4e000, 0x100), 179 DEFINE_RES_IRQ(gic_iid(0x5d)), 180 }; 181 182 void __init r8a7778_add_mmc_device(struct sh_mmcif_plat_data *info) 183 { 184 platform_device_register_resndata( 185 &platform_bus, "sh_mmcif", -1, 186 mmc_resources, ARRAY_SIZE(mmc_resources), 187 info, sizeof(*info)); 188 } 189 190 void __init r8a7778_add_standard_devices(void) 191 { 192 int i; 193 194 #ifdef CONFIG_CACHE_L2X0 195 void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); 196 if (base) { 197 /* 198 * Early BRESP enable, Shared attribute override enable, 64K*16way 199 * don't call iounmap(base) 200 */ 201 l2x0_init(base, 0x40470000, 0x82000fff); 202 } 203 #endif 204 205 for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++) 206 platform_device_register_data(&platform_bus, "sh-sci", i, 207 &scif_platform_data[i], 208 sizeof(struct plat_sci_port)); 209 210 r8a7778_register_tmu(0); 211 r8a7778_register_tmu(1); 212 } 213 214 static struct renesas_intc_irqpin_config irqpin_platform_data = { 215 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ 216 .sense_bitfield_width = 2, 217 }; 218 219 static struct resource irqpin_resources[] = { 220 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ 221 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ 222 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ 223 DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ 224 DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ 225 DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */ 226 DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */ 227 DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */ 228 DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */ 229 }; 230 231 void __init r8a7778_init_irq_extpin(int irlm) 232 { 233 void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); 234 unsigned long tmp; 235 236 if (!icr0) { 237 pr_warn("r8a7778: unable to setup external irq pin mode\n"); 238 return; 239 } 240 241 tmp = ioread32(icr0); 242 if (irlm) 243 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ 244 else 245 tmp &= ~(1 << 23); /* IRL mode - not supported */ 246 tmp |= (1 << 21); /* LVLMODE = 1 */ 247 iowrite32(tmp, icr0); 248 iounmap(icr0); 249 250 if (irlm) 251 platform_device_register_resndata( 252 &platform_bus, "renesas_intc_irqpin", -1, 253 irqpin_resources, ARRAY_SIZE(irqpin_resources), 254 &irqpin_platform_data, sizeof(irqpin_platform_data)); 255 } 256 257 #define INT2SMSKCR0 0x82288 /* 0xfe782288 */ 258 #define INT2SMSKCR1 0x8228c /* 0xfe78228c */ 259 260 #define INT2NTSR0 0x00018 /* 0xfe700018 */ 261 #define INT2NTSR1 0x0002c /* 0xfe70002c */ 262 static void __init r8a7778_init_irq_common(void) 263 { 264 void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000); 265 266 BUG_ON(!base); 267 268 /* route all interrupts to ARM */ 269 __raw_writel(0x73ffffff, base + INT2NTSR0); 270 __raw_writel(0xffffffff, base + INT2NTSR1); 271 272 /* unmask all known interrupts in INTCS2 */ 273 __raw_writel(0x08330773, base + INT2SMSKCR0); 274 __raw_writel(0x00311110, base + INT2SMSKCR1); 275 276 iounmap(base); 277 } 278 279 void __init r8a7778_init_irq(void) 280 { 281 void __iomem *gic_dist_base; 282 void __iomem *gic_cpu_base; 283 284 gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE); 285 gic_cpu_base = ioremap_nocache(0xfe430000, PAGE_SIZE); 286 BUG_ON(!gic_dist_base || !gic_cpu_base); 287 288 /* use GIC to handle interrupts */ 289 gic_init(0, 29, gic_dist_base, gic_cpu_base); 290 291 r8a7778_init_irq_common(); 292 } 293 294 void __init r8a7778_init_delay(void) 295 { 296 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ 297 } 298 299 #ifdef CONFIG_USE_OF 300 void __init r8a7778_init_irq_dt(void) 301 { 302 irqchip_init(); 303 r8a7778_init_irq_common(); 304 } 305 306 static const struct of_dev_auxdata r8a7778_auxdata_lookup[] __initconst = { 307 {}, 308 }; 309 310 void __init r8a7778_add_standard_devices_dt(void) 311 { 312 of_platform_populate(NULL, of_default_bus_match_table, 313 r8a7778_auxdata_lookup, NULL); 314 } 315 316 static const char *r8a7778_compat_dt[] __initdata = { 317 "renesas,r8a7778", 318 NULL, 319 }; 320 321 DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") 322 .init_early = r8a7778_init_delay, 323 .init_irq = r8a7778_init_irq_dt, 324 .init_machine = r8a7778_add_standard_devices_dt, 325 .init_time = shmobile_timer_init, 326 .dt_compat = r8a7778_compat_dt, 327 MACHINE_END 328 329 #endif /* CONFIG_USE_OF */ 330