1 /* 2 * r8a7778 processor support 3 * 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 * Copyright (C) 2013 Cogent Embedded, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/io.h> 24 #include <linux/irqchip/arm-gic.h> 25 #include <linux/of.h> 26 #include <linux/of_platform.h> 27 #include <linux/platform_data/dma-rcar-hpbdma.h> 28 #include <linux/platform_data/gpio-rcar.h> 29 #include <linux/platform_data/irq-renesas-intc-irqpin.h> 30 #include <linux/platform_device.h> 31 #include <linux/irqchip.h> 32 #include <linux/serial_sci.h> 33 #include <linux/sh_timer.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/usb/phy.h> 36 #include <linux/usb/hcd.h> 37 #include <linux/usb/ehci_pdriver.h> 38 #include <linux/usb/ohci_pdriver.h> 39 #include <linux/dma-mapping.h> 40 #include <mach/irqs.h> 41 #include <mach/r8a7778.h> 42 #include <mach/common.h> 43 #include <asm/mach/arch.h> 44 #include <asm/hardware/cache-l2x0.h> 45 46 /* SCIF */ 47 #define R8A7778_SCIF(index, baseaddr, irq) \ 48 static struct plat_sci_port scif##index##_platform_data = { \ 49 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 50 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ 51 .scbrr_algo_id = SCBRR_ALGO_2, \ 52 .type = PORT_SCIF, \ 53 }; \ 54 \ 55 static struct resource scif##index##_resources[] = { \ 56 DEFINE_RES_MEM(baseaddr, 0x100), \ 57 DEFINE_RES_IRQ(irq), \ 58 } 59 60 R8A7778_SCIF(0, 0xffe40000, gic_iid(0x66)); 61 R8A7778_SCIF(1, 0xffe41000, gic_iid(0x67)); 62 R8A7778_SCIF(2, 0xffe42000, gic_iid(0x68)); 63 R8A7778_SCIF(3, 0xffe43000, gic_iid(0x69)); 64 R8A7778_SCIF(4, 0xffe44000, gic_iid(0x6a)); 65 R8A7778_SCIF(5, 0xffe45000, gic_iid(0x6b)); 66 67 #define r8a7778_register_scif(index) \ 68 platform_device_register_resndata(&platform_bus, "sh-sci", index, \ 69 scif##index##_resources, \ 70 ARRAY_SIZE(scif##index##_resources), \ 71 &scif##index##_platform_data, \ 72 sizeof(scif##index##_platform_data)) 73 74 /* TMU */ 75 static struct resource sh_tmu0_resources[] __initdata = { 76 DEFINE_RES_MEM(0xffd80008, 12), 77 DEFINE_RES_IRQ(gic_iid(0x40)), 78 }; 79 80 static struct sh_timer_config sh_tmu0_platform_data __initdata = { 81 .name = "TMU00", 82 .channel_offset = 0x4, 83 .timer_bit = 0, 84 .clockevent_rating = 200, 85 }; 86 87 static struct resource sh_tmu1_resources[] __initdata = { 88 DEFINE_RES_MEM(0xffd80014, 12), 89 DEFINE_RES_IRQ(gic_iid(0x41)), 90 }; 91 92 static struct sh_timer_config sh_tmu1_platform_data __initdata = { 93 .name = "TMU01", 94 .channel_offset = 0x10, 95 .timer_bit = 1, 96 .clocksource_rating = 200, 97 }; 98 99 #define r8a7778_register_tmu(idx) \ 100 platform_device_register_resndata( \ 101 &platform_bus, "sh_tmu", idx, \ 102 sh_tmu##idx##_resources, \ 103 ARRAY_SIZE(sh_tmu##idx##_resources), \ 104 &sh_tmu##idx##_platform_data, \ 105 sizeof(sh_tmu##idx##_platform_data)) 106 107 int r8a7778_usb_phy_power(bool enable) 108 { 109 static struct usb_phy *phy = NULL; 110 int ret = 0; 111 112 if (!phy) 113 phy = usb_get_phy(USB_PHY_TYPE_USB2); 114 115 if (IS_ERR(phy)) { 116 pr_err("kernel doesn't have usb phy driver\n"); 117 return PTR_ERR(phy); 118 } 119 120 if (enable) 121 ret = usb_phy_init(phy); 122 else 123 usb_phy_shutdown(phy); 124 125 return ret; 126 } 127 128 /* USB */ 129 static int usb_power_on(struct platform_device *pdev) 130 { 131 int ret = r8a7778_usb_phy_power(true); 132 133 if (ret) 134 return ret; 135 136 pm_runtime_enable(&pdev->dev); 137 pm_runtime_get_sync(&pdev->dev); 138 139 return 0; 140 } 141 142 static void usb_power_off(struct platform_device *pdev) 143 { 144 if (r8a7778_usb_phy_power(false)) 145 return; 146 147 pm_runtime_put_sync(&pdev->dev); 148 pm_runtime_disable(&pdev->dev); 149 } 150 151 static int ehci_init_internal_buffer(struct usb_hcd *hcd) 152 { 153 /* 154 * Below are recommended values from the datasheet; 155 * see [USB :: Setting of EHCI Internal Buffer]. 156 */ 157 /* EHCI IP internal buffer setting */ 158 iowrite32(0x00ff0040, hcd->regs + 0x0094); 159 /* EHCI IP internal buffer enable */ 160 iowrite32(0x00000001, hcd->regs + 0x009C); 161 162 return 0; 163 } 164 165 static struct usb_ehci_pdata ehci_pdata __initdata = { 166 .power_on = usb_power_on, 167 .power_off = usb_power_off, 168 .power_suspend = usb_power_off, 169 .pre_setup = ehci_init_internal_buffer, 170 }; 171 172 static struct resource ehci_resources[] __initdata = { 173 DEFINE_RES_MEM(0xffe70000, 0x400), 174 DEFINE_RES_IRQ(gic_iid(0x4c)), 175 }; 176 177 static struct usb_ohci_pdata ohci_pdata __initdata = { 178 .power_on = usb_power_on, 179 .power_off = usb_power_off, 180 .power_suspend = usb_power_off, 181 }; 182 183 static struct resource ohci_resources[] __initdata = { 184 DEFINE_RES_MEM(0xffe70400, 0x400), 185 DEFINE_RES_IRQ(gic_iid(0x4c)), 186 }; 187 188 #define USB_PLATFORM_INFO(hci) \ 189 static struct platform_device_info hci##_info __initdata = { \ 190 .parent = &platform_bus, \ 191 .name = #hci "-platform", \ 192 .id = -1, \ 193 .res = hci##_resources, \ 194 .num_res = ARRAY_SIZE(hci##_resources), \ 195 .data = &hci##_pdata, \ 196 .size_data = sizeof(hci##_pdata), \ 197 .dma_mask = DMA_BIT_MASK(32), \ 198 } 199 200 USB_PLATFORM_INFO(ehci); 201 USB_PLATFORM_INFO(ohci); 202 203 /* PFC/GPIO */ 204 static struct resource pfc_resources[] __initdata = { 205 DEFINE_RES_MEM(0xfffc0000, 0x118), 206 }; 207 208 #define R8A7778_GPIO(idx) \ 209 static struct resource r8a7778_gpio##idx##_resources[] __initdata = { \ 210 DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30), \ 211 DEFINE_RES_IRQ(gic_iid(0x87)), \ 212 }; \ 213 \ 214 static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data __initdata = { \ 215 .gpio_base = 32 * (idx), \ 216 .irq_base = GPIO_IRQ_BASE(idx), \ 217 .number_of_pins = 32, \ 218 .pctl_name = "pfc-r8a7778", \ 219 } 220 221 R8A7778_GPIO(0); 222 R8A7778_GPIO(1); 223 R8A7778_GPIO(2); 224 R8A7778_GPIO(3); 225 R8A7778_GPIO(4); 226 227 #define r8a7778_register_gpio(idx) \ 228 platform_device_register_resndata( \ 229 &platform_bus, "gpio_rcar", idx, \ 230 r8a7778_gpio##idx##_resources, \ 231 ARRAY_SIZE(r8a7778_gpio##idx##_resources), \ 232 &r8a7778_gpio##idx##_platform_data, \ 233 sizeof(r8a7778_gpio##idx##_platform_data)) 234 235 void __init r8a7778_pinmux_init(void) 236 { 237 platform_device_register_simple( 238 "pfc-r8a7778", -1, 239 pfc_resources, 240 ARRAY_SIZE(pfc_resources)); 241 242 r8a7778_register_gpio(0); 243 r8a7778_register_gpio(1); 244 r8a7778_register_gpio(2); 245 r8a7778_register_gpio(3); 246 r8a7778_register_gpio(4); 247 }; 248 249 /* I2C */ 250 static struct resource i2c_resources[] __initdata = { 251 /* I2C0 */ 252 DEFINE_RES_MEM(0xffc70000, 0x1000), 253 DEFINE_RES_IRQ(gic_iid(0x63)), 254 /* I2C1 */ 255 DEFINE_RES_MEM(0xffc71000, 0x1000), 256 DEFINE_RES_IRQ(gic_iid(0x6e)), 257 /* I2C2 */ 258 DEFINE_RES_MEM(0xffc72000, 0x1000), 259 DEFINE_RES_IRQ(gic_iid(0x6c)), 260 /* I2C3 */ 261 DEFINE_RES_MEM(0xffc73000, 0x1000), 262 DEFINE_RES_IRQ(gic_iid(0x6d)), 263 }; 264 265 static void __init r8a7778_register_i2c(int id) 266 { 267 BUG_ON(id < 0 || id > 3); 268 269 platform_device_register_simple( 270 "i2c-rcar", id, 271 i2c_resources + (2 * id), 2); 272 } 273 274 /* HSPI */ 275 static struct resource hspi_resources[] __initdata = { 276 /* HSPI0 */ 277 DEFINE_RES_MEM(0xfffc7000, 0x18), 278 DEFINE_RES_IRQ(gic_iid(0x5f)), 279 /* HSPI1 */ 280 DEFINE_RES_MEM(0xfffc8000, 0x18), 281 DEFINE_RES_IRQ(gic_iid(0x74)), 282 /* HSPI2 */ 283 DEFINE_RES_MEM(0xfffc6000, 0x18), 284 DEFINE_RES_IRQ(gic_iid(0x75)), 285 }; 286 287 static void __init r8a7778_register_hspi(int id) 288 { 289 BUG_ON(id < 0 || id > 2); 290 291 platform_device_register_simple( 292 "sh-hspi", id, 293 hspi_resources + (2 * id), 2); 294 } 295 296 void __init r8a7778_add_dt_devices(void) 297 { 298 #ifdef CONFIG_CACHE_L2X0 299 void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); 300 if (base) { 301 /* 302 * Early BRESP enable, Shared attribute override enable, 64K*16way 303 * don't call iounmap(base) 304 */ 305 l2x0_init(base, 0x40470000, 0x82000fff); 306 } 307 #endif 308 309 r8a7778_register_scif(0); 310 r8a7778_register_scif(1); 311 r8a7778_register_scif(2); 312 r8a7778_register_scif(3); 313 r8a7778_register_scif(4); 314 r8a7778_register_scif(5); 315 r8a7778_register_tmu(0); 316 r8a7778_register_tmu(1); 317 } 318 319 /* HPB-DMA */ 320 321 /* Asynchronous mode register (ASYNCMDR) bits */ 322 #define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(2) /* SDHI0 */ 323 #define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(2) /* SDHI0 */ 324 #define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */ 325 #define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(1) /* SDHI0 */ 326 #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1) /* SDHI0 */ 327 #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */ 328 329 #define HPBDMA_SSI(_id) \ 330 { \ 331 .id = HPBDMA_SLAVE_SSI## _id ##_TX, \ 332 .addr = 0xffd91008 + (_id * 0x40), \ 333 .dcr = HPB_DMAE_DCR_CT | \ 334 HPB_DMAE_DCR_DIP | \ 335 HPB_DMAE_DCR_SPDS_32BIT | \ 336 HPB_DMAE_DCR_DMDL | \ 337 HPB_DMAE_DCR_DPDS_32BIT, \ 338 .port = _id + (_id << 8), \ 339 .dma_ch = (28 + _id), \ 340 }, { \ 341 .id = HPBDMA_SLAVE_SSI## _id ##_RX, \ 342 .addr = 0xffd9100c + (_id * 0x40), \ 343 .dcr = HPB_DMAE_DCR_CT | \ 344 HPB_DMAE_DCR_DIP | \ 345 HPB_DMAE_DCR_SMDL | \ 346 HPB_DMAE_DCR_SPDS_32BIT | \ 347 HPB_DMAE_DCR_DPDS_32BIT, \ 348 .port = _id + (_id << 8), \ 349 .dma_ch = (28 + _id), \ 350 } 351 352 #define HPBDMA_HPBIF(_id) \ 353 { \ 354 .id = HPBDMA_SLAVE_HPBIF## _id ##_TX, \ 355 .addr = 0xffda0000 + (_id * 0x1000), \ 356 .dcr = HPB_DMAE_DCR_CT | \ 357 HPB_DMAE_DCR_DIP | \ 358 HPB_DMAE_DCR_SPDS_32BIT | \ 359 HPB_DMAE_DCR_DMDL | \ 360 HPB_DMAE_DCR_DPDS_32BIT, \ 361 .port = 0x1111, \ 362 .dma_ch = (28 + _id), \ 363 }, { \ 364 .id = HPBDMA_SLAVE_HPBIF## _id ##_RX, \ 365 .addr = 0xffda0000 + (_id * 0x1000), \ 366 .dcr = HPB_DMAE_DCR_CT | \ 367 HPB_DMAE_DCR_DIP | \ 368 HPB_DMAE_DCR_SMDL | \ 369 HPB_DMAE_DCR_SPDS_32BIT | \ 370 HPB_DMAE_DCR_DPDS_32BIT, \ 371 .port = 0x1111, \ 372 .dma_ch = (28 + _id), \ 373 } 374 375 static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = { 376 { 377 .id = HPBDMA_SLAVE_SDHI0_TX, 378 .addr = 0xffe4c000 + 0x30, 379 .dcr = HPB_DMAE_DCR_SPDS_16BIT | 380 HPB_DMAE_DCR_DMDL | 381 HPB_DMAE_DCR_DPDS_16BIT, 382 .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | 383 HPB_DMAE_ASYNCRSTR_ASRST22 | 384 HPB_DMAE_ASYNCRSTR_ASRST23, 385 .mdr = HPB_DMAE_ASYNCMDR_ASMD21_MULTI, 386 .mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK, 387 .port = 0x0D0C, 388 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, 389 .dma_ch = 21, 390 }, { 391 .id = HPBDMA_SLAVE_SDHI0_RX, 392 .addr = 0xffe4c000 + 0x30, 393 .dcr = HPB_DMAE_DCR_SMDL | 394 HPB_DMAE_DCR_SPDS_16BIT | 395 HPB_DMAE_DCR_DPDS_16BIT, 396 .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | 397 HPB_DMAE_ASYNCRSTR_ASRST22 | 398 HPB_DMAE_ASYNCRSTR_ASRST23, 399 .mdr = HPB_DMAE_ASYNCMDR_ASMD22_MULTI, 400 .mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK, 401 .port = 0x0D0C, 402 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, 403 .dma_ch = 22, 404 }, { 405 .id = HPBDMA_SLAVE_USBFUNC_TX, /* for D0 */ 406 .addr = 0xffe60018, 407 .dcr = HPB_DMAE_DCR_SPDS_32BIT | 408 HPB_DMAE_DCR_DMDL | 409 HPB_DMAE_DCR_DPDS_32BIT, 410 .port = 0x0000, 411 .dma_ch = 14, 412 }, { 413 .id = HPBDMA_SLAVE_USBFUNC_RX, /* for D1 */ 414 .addr = 0xffe6001c, 415 .dcr = HPB_DMAE_DCR_SMDL | 416 HPB_DMAE_DCR_SPDS_32BIT | 417 HPB_DMAE_DCR_DPDS_32BIT, 418 .port = 0x0101, 419 .dma_ch = 15, 420 }, 421 422 HPBDMA_SSI(0), 423 HPBDMA_SSI(1), 424 HPBDMA_SSI(2), 425 HPBDMA_SSI(3), 426 HPBDMA_SSI(4), 427 HPBDMA_SSI(5), 428 HPBDMA_SSI(6), 429 HPBDMA_SSI(7), 430 HPBDMA_SSI(8), 431 432 HPBDMA_HPBIF(0), 433 HPBDMA_HPBIF(1), 434 HPBDMA_HPBIF(2), 435 HPBDMA_HPBIF(3), 436 HPBDMA_HPBIF(4), 437 HPBDMA_HPBIF(5), 438 HPBDMA_HPBIF(6), 439 HPBDMA_HPBIF(7), 440 HPBDMA_HPBIF(8), 441 }; 442 443 static const struct hpb_dmae_channel hpb_dmae_channels[] = { 444 HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_TX), /* ch. 14 */ 445 HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_RX), /* ch. 15 */ 446 HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */ 447 HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */ 448 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_TX), /* ch. 28 */ 449 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_RX), /* ch. 28 */ 450 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_TX), /* ch. 28 */ 451 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_RX), /* ch. 28 */ 452 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_TX), /* ch. 29 */ 453 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_RX), /* ch. 29 */ 454 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_TX), /* ch. 29 */ 455 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_RX), /* ch. 29 */ 456 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_TX), /* ch. 30 */ 457 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_RX), /* ch. 30 */ 458 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_TX), /* ch. 30 */ 459 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_RX), /* ch. 30 */ 460 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_TX), /* ch. 31 */ 461 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_RX), /* ch. 31 */ 462 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_TX), /* ch. 31 */ 463 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_RX), /* ch. 31 */ 464 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_TX), /* ch. 32 */ 465 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_RX), /* ch. 32 */ 466 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_TX), /* ch. 32 */ 467 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_RX), /* ch. 32 */ 468 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_TX), /* ch. 33 */ 469 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_RX), /* ch. 33 */ 470 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_TX), /* ch. 33 */ 471 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_RX), /* ch. 33 */ 472 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_TX), /* ch. 34 */ 473 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_RX), /* ch. 34 */ 474 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_TX), /* ch. 34 */ 475 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_RX), /* ch. 34 */ 476 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_TX), /* ch. 35 */ 477 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_RX), /* ch. 35 */ 478 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_TX), /* ch. 35 */ 479 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_RX), /* ch. 35 */ 480 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_TX), /* ch. 36 */ 481 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_RX), /* ch. 36 */ 482 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_TX), /* ch. 36 */ 483 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_RX), /* ch. 36 */ 484 }; 485 486 static struct hpb_dmae_pdata dma_platform_data __initdata = { 487 .slaves = hpb_dmae_slaves, 488 .num_slaves = ARRAY_SIZE(hpb_dmae_slaves), 489 .channels = hpb_dmae_channels, 490 .num_channels = ARRAY_SIZE(hpb_dmae_channels), 491 .ts_shift = { 492 [XMIT_SZ_8BIT] = 0, 493 [XMIT_SZ_16BIT] = 1, 494 [XMIT_SZ_32BIT] = 2, 495 }, 496 .num_hw_channels = 39, 497 }; 498 499 static struct resource hpb_dmae_resources[] __initdata = { 500 /* Channel registers */ 501 DEFINE_RES_MEM(0xffc08000, 0x1000), 502 /* Common registers */ 503 DEFINE_RES_MEM(0xffc09000, 0x170), 504 /* Asynchronous reset registers */ 505 DEFINE_RES_MEM(0xffc00300, 4), 506 /* Asynchronous mode registers */ 507 DEFINE_RES_MEM(0xffc00400, 4), 508 /* IRQ for DMA channels */ 509 DEFINE_RES_NAMED(gic_iid(0x7b), 5, NULL, IORESOURCE_IRQ), 510 }; 511 512 static void __init r8a7778_register_hpb_dmae(void) 513 { 514 platform_device_register_resndata(&platform_bus, "hpb-dma-engine", -1, 515 hpb_dmae_resources, 516 ARRAY_SIZE(hpb_dmae_resources), 517 &dma_platform_data, 518 sizeof(dma_platform_data)); 519 } 520 521 void __init r8a7778_add_standard_devices(void) 522 { 523 r8a7778_add_dt_devices(); 524 r8a7778_register_i2c(0); 525 r8a7778_register_i2c(1); 526 r8a7778_register_i2c(2); 527 r8a7778_register_i2c(3); 528 r8a7778_register_hspi(0); 529 r8a7778_register_hspi(1); 530 r8a7778_register_hspi(2); 531 532 r8a7778_register_hpb_dmae(); 533 } 534 535 void __init r8a7778_init_late(void) 536 { 537 platform_device_register_full(&ehci_info); 538 platform_device_register_full(&ohci_info); 539 } 540 541 static struct renesas_intc_irqpin_config irqpin_platform_data __initdata = { 542 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ 543 .sense_bitfield_width = 2, 544 }; 545 546 static struct resource irqpin_resources[] __initdata = { 547 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ 548 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ 549 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ 550 DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ 551 DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ 552 DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */ 553 DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */ 554 DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */ 555 DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */ 556 }; 557 558 void __init r8a7778_init_irq_extpin_dt(int irlm) 559 { 560 void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); 561 unsigned long tmp; 562 563 if (!icr0) { 564 pr_warn("r8a7778: unable to setup external irq pin mode\n"); 565 return; 566 } 567 568 tmp = ioread32(icr0); 569 if (irlm) 570 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ 571 else 572 tmp &= ~(1 << 23); /* IRL mode - not supported */ 573 tmp |= (1 << 21); /* LVLMODE = 1 */ 574 iowrite32(tmp, icr0); 575 iounmap(icr0); 576 } 577 578 void __init r8a7778_init_irq_extpin(int irlm) 579 { 580 r8a7778_init_irq_extpin_dt(irlm); 581 if (irlm) 582 platform_device_register_resndata( 583 &platform_bus, "renesas_intc_irqpin", -1, 584 irqpin_resources, ARRAY_SIZE(irqpin_resources), 585 &irqpin_platform_data, sizeof(irqpin_platform_data)); 586 } 587 588 void __init r8a7778_init_delay(void) 589 { 590 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ 591 } 592 593 #ifdef CONFIG_USE_OF 594 #define INT2SMSKCR0 0x82288 /* 0xfe782288 */ 595 #define INT2SMSKCR1 0x8228c /* 0xfe78228c */ 596 597 #define INT2NTSR0 0x00018 /* 0xfe700018 */ 598 #define INT2NTSR1 0x0002c /* 0xfe70002c */ 599 void __init r8a7778_init_irq_dt(void) 600 { 601 void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000); 602 603 BUG_ON(!base); 604 605 irqchip_init(); 606 607 /* route all interrupts to ARM */ 608 __raw_writel(0x73ffffff, base + INT2NTSR0); 609 __raw_writel(0xffffffff, base + INT2NTSR1); 610 611 /* unmask all known interrupts in INTCS2 */ 612 __raw_writel(0x08330773, base + INT2SMSKCR0); 613 __raw_writel(0x00311110, base + INT2SMSKCR1); 614 615 iounmap(base); 616 } 617 618 static const char *r8a7778_compat_dt[] __initdata = { 619 "renesas,r8a7778", 620 NULL, 621 }; 622 623 DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") 624 .init_early = r8a7778_init_delay, 625 .init_irq = r8a7778_init_irq_dt, 626 .dt_compat = r8a7778_compat_dt, 627 .init_late = r8a7778_init_late, 628 MACHINE_END 629 630 #endif /* CONFIG_USE_OF */ 631