1 /* 2 * r8a7778 processor support 3 * 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 * Copyright (C) 2013 Cogent Embedded, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/io.h> 20 #include <linux/irqchip/arm-gic.h> 21 #include <linux/of.h> 22 #include <linux/of_platform.h> 23 #include <linux/platform_data/dma-rcar-hpbdma.h> 24 #include <linux/platform_data/gpio-rcar.h> 25 #include <linux/platform_data/irq-renesas-intc-irqpin.h> 26 #include <linux/platform_device.h> 27 #include <linux/irqchip.h> 28 #include <linux/serial_sci.h> 29 #include <linux/sh_timer.h> 30 #include <linux/pm_runtime.h> 31 #include <linux/usb/phy.h> 32 #include <linux/usb/hcd.h> 33 #include <linux/usb/ehci_pdriver.h> 34 #include <linux/usb/ohci_pdriver.h> 35 #include <linux/dma-mapping.h> 36 37 #include <asm/mach/arch.h> 38 #include <asm/hardware/cache-l2x0.h> 39 40 #include "common.h" 41 #include "irqs.h" 42 #include "r8a7778.h" 43 44 /* SCIF */ 45 #define R8A7778_SCIF(index, baseaddr, irq) \ 46 static struct plat_sci_port scif##index##_platform_data = { \ 47 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 48 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ 49 .type = PORT_SCIF, \ 50 }; \ 51 \ 52 static struct resource scif##index##_resources[] = { \ 53 DEFINE_RES_MEM(baseaddr, 0x100), \ 54 DEFINE_RES_IRQ(irq), \ 55 } 56 57 R8A7778_SCIF(0, 0xffe40000, gic_iid(0x66)); 58 R8A7778_SCIF(1, 0xffe41000, gic_iid(0x67)); 59 R8A7778_SCIF(2, 0xffe42000, gic_iid(0x68)); 60 R8A7778_SCIF(3, 0xffe43000, gic_iid(0x69)); 61 R8A7778_SCIF(4, 0xffe44000, gic_iid(0x6a)); 62 R8A7778_SCIF(5, 0xffe45000, gic_iid(0x6b)); 63 64 #define r8a7778_register_scif(index) \ 65 platform_device_register_resndata(NULL, "sh-sci", index, \ 66 scif##index##_resources, \ 67 ARRAY_SIZE(scif##index##_resources), \ 68 &scif##index##_platform_data, \ 69 sizeof(scif##index##_platform_data)) 70 71 /* TMU */ 72 static struct sh_timer_config sh_tmu0_platform_data = { 73 .channels_mask = 7, 74 }; 75 76 static struct resource sh_tmu0_resources[] = { 77 DEFINE_RES_MEM(0xffd80000, 0x30), 78 DEFINE_RES_IRQ(gic_iid(0x40)), 79 DEFINE_RES_IRQ(gic_iid(0x41)), 80 DEFINE_RES_IRQ(gic_iid(0x42)), 81 }; 82 83 #define r8a7778_register_tmu(idx) \ 84 platform_device_register_resndata( \ 85 NULL, "sh-tmu", idx, \ 86 sh_tmu##idx##_resources, \ 87 ARRAY_SIZE(sh_tmu##idx##_resources), \ 88 &sh_tmu##idx##_platform_data, \ 89 sizeof(sh_tmu##idx##_platform_data)) 90 91 int r8a7778_usb_phy_power(bool enable) 92 { 93 static struct usb_phy *phy = NULL; 94 int ret = 0; 95 96 if (!phy) 97 phy = usb_get_phy(USB_PHY_TYPE_USB2); 98 99 if (IS_ERR(phy)) { 100 pr_err("kernel doesn't have usb phy driver\n"); 101 return PTR_ERR(phy); 102 } 103 104 if (enable) 105 ret = usb_phy_init(phy); 106 else 107 usb_phy_shutdown(phy); 108 109 return ret; 110 } 111 112 /* USB */ 113 static int usb_power_on(struct platform_device *pdev) 114 { 115 int ret = r8a7778_usb_phy_power(true); 116 117 if (ret) 118 return ret; 119 120 pm_runtime_enable(&pdev->dev); 121 pm_runtime_get_sync(&pdev->dev); 122 123 return 0; 124 } 125 126 static void usb_power_off(struct platform_device *pdev) 127 { 128 if (r8a7778_usb_phy_power(false)) 129 return; 130 131 pm_runtime_put_sync(&pdev->dev); 132 pm_runtime_disable(&pdev->dev); 133 } 134 135 static int ehci_init_internal_buffer(struct usb_hcd *hcd) 136 { 137 /* 138 * Below are recommended values from the datasheet; 139 * see [USB :: Setting of EHCI Internal Buffer]. 140 */ 141 /* EHCI IP internal buffer setting */ 142 iowrite32(0x00ff0040, hcd->regs + 0x0094); 143 /* EHCI IP internal buffer enable */ 144 iowrite32(0x00000001, hcd->regs + 0x009C); 145 146 return 0; 147 } 148 149 static struct usb_ehci_pdata ehci_pdata __initdata = { 150 .power_on = usb_power_on, 151 .power_off = usb_power_off, 152 .power_suspend = usb_power_off, 153 .pre_setup = ehci_init_internal_buffer, 154 }; 155 156 static struct resource ehci_resources[] __initdata = { 157 DEFINE_RES_MEM(0xffe70000, 0x400), 158 DEFINE_RES_IRQ(gic_iid(0x4c)), 159 }; 160 161 static struct usb_ohci_pdata ohci_pdata __initdata = { 162 .power_on = usb_power_on, 163 .power_off = usb_power_off, 164 .power_suspend = usb_power_off, 165 }; 166 167 static struct resource ohci_resources[] __initdata = { 168 DEFINE_RES_MEM(0xffe70400, 0x400), 169 DEFINE_RES_IRQ(gic_iid(0x4c)), 170 }; 171 172 #define USB_PLATFORM_INFO(hci) \ 173 static struct platform_device_info hci##_info __initdata = { \ 174 .name = #hci "-platform", \ 175 .id = -1, \ 176 .res = hci##_resources, \ 177 .num_res = ARRAY_SIZE(hci##_resources), \ 178 .data = &hci##_pdata, \ 179 .size_data = sizeof(hci##_pdata), \ 180 .dma_mask = DMA_BIT_MASK(32), \ 181 } 182 183 USB_PLATFORM_INFO(ehci); 184 USB_PLATFORM_INFO(ohci); 185 186 /* PFC/GPIO */ 187 static struct resource pfc_resources[] __initdata = { 188 DEFINE_RES_MEM(0xfffc0000, 0x118), 189 }; 190 191 #define R8A7778_GPIO(idx) \ 192 static struct resource r8a7778_gpio##idx##_resources[] __initdata = { \ 193 DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30), \ 194 DEFINE_RES_IRQ(gic_iid(0x87)), \ 195 }; \ 196 \ 197 static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data __initdata = { \ 198 .gpio_base = 32 * (idx), \ 199 .irq_base = GPIO_IRQ_BASE(idx), \ 200 .number_of_pins = 32, \ 201 .pctl_name = "pfc-r8a7778", \ 202 } 203 204 R8A7778_GPIO(0); 205 R8A7778_GPIO(1); 206 R8A7778_GPIO(2); 207 R8A7778_GPIO(3); 208 R8A7778_GPIO(4); 209 210 #define r8a7778_register_gpio(idx) \ 211 platform_device_register_resndata( \ 212 NULL, "gpio_rcar", idx, \ 213 r8a7778_gpio##idx##_resources, \ 214 ARRAY_SIZE(r8a7778_gpio##idx##_resources), \ 215 &r8a7778_gpio##idx##_platform_data, \ 216 sizeof(r8a7778_gpio##idx##_platform_data)) 217 218 void __init r8a7778_pinmux_init(void) 219 { 220 platform_device_register_simple( 221 "pfc-r8a7778", -1, 222 pfc_resources, 223 ARRAY_SIZE(pfc_resources)); 224 225 r8a7778_register_gpio(0); 226 r8a7778_register_gpio(1); 227 r8a7778_register_gpio(2); 228 r8a7778_register_gpio(3); 229 r8a7778_register_gpio(4); 230 }; 231 232 /* I2C */ 233 static struct resource i2c_resources[] __initdata = { 234 /* I2C0 */ 235 DEFINE_RES_MEM(0xffc70000, 0x1000), 236 DEFINE_RES_IRQ(gic_iid(0x63)), 237 /* I2C1 */ 238 DEFINE_RES_MEM(0xffc71000, 0x1000), 239 DEFINE_RES_IRQ(gic_iid(0x6e)), 240 /* I2C2 */ 241 DEFINE_RES_MEM(0xffc72000, 0x1000), 242 DEFINE_RES_IRQ(gic_iid(0x6c)), 243 /* I2C3 */ 244 DEFINE_RES_MEM(0xffc73000, 0x1000), 245 DEFINE_RES_IRQ(gic_iid(0x6d)), 246 }; 247 248 static void __init r8a7778_register_i2c(int id) 249 { 250 BUG_ON(id < 0 || id > 3); 251 252 platform_device_register_simple( 253 "i2c-rcar", id, 254 i2c_resources + (2 * id), 2); 255 } 256 257 /* HSPI */ 258 static struct resource hspi_resources[] __initdata = { 259 /* HSPI0 */ 260 DEFINE_RES_MEM(0xfffc7000, 0x18), 261 DEFINE_RES_IRQ(gic_iid(0x5f)), 262 /* HSPI1 */ 263 DEFINE_RES_MEM(0xfffc8000, 0x18), 264 DEFINE_RES_IRQ(gic_iid(0x74)), 265 /* HSPI2 */ 266 DEFINE_RES_MEM(0xfffc6000, 0x18), 267 DEFINE_RES_IRQ(gic_iid(0x75)), 268 }; 269 270 static void __init r8a7778_register_hspi(int id) 271 { 272 BUG_ON(id < 0 || id > 2); 273 274 platform_device_register_simple( 275 "sh-hspi", id, 276 hspi_resources + (2 * id), 2); 277 } 278 279 void __init r8a7778_add_dt_devices(void) 280 { 281 #ifdef CONFIG_CACHE_L2X0 282 void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); 283 if (base) { 284 /* 285 * Shared attribute override enable, 64K*16way 286 * don't call iounmap(base) 287 */ 288 l2x0_init(base, 0x00400000, 0xc20f0fff); 289 } 290 #endif 291 } 292 293 /* HPB-DMA */ 294 295 /* Asynchronous mode register (ASYNCMDR) bits */ 296 #define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(2) /* SDHI0 */ 297 #define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(2) /* SDHI0 */ 298 #define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */ 299 #define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(1) /* SDHI0 */ 300 #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1) /* SDHI0 */ 301 #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */ 302 303 #define HPBDMA_SSI(_id) \ 304 { \ 305 .id = HPBDMA_SLAVE_SSI## _id ##_TX, \ 306 .addr = 0xffd91008 + (_id * 0x40), \ 307 .dcr = HPB_DMAE_DCR_CT | \ 308 HPB_DMAE_DCR_DIP | \ 309 HPB_DMAE_DCR_SPDS_32BIT | \ 310 HPB_DMAE_DCR_DMDL | \ 311 HPB_DMAE_DCR_DPDS_32BIT, \ 312 .port = _id + (_id << 8), \ 313 .dma_ch = (28 + _id), \ 314 }, { \ 315 .id = HPBDMA_SLAVE_SSI## _id ##_RX, \ 316 .addr = 0xffd9100c + (_id * 0x40), \ 317 .dcr = HPB_DMAE_DCR_CT | \ 318 HPB_DMAE_DCR_DIP | \ 319 HPB_DMAE_DCR_SMDL | \ 320 HPB_DMAE_DCR_SPDS_32BIT | \ 321 HPB_DMAE_DCR_DPDS_32BIT, \ 322 .port = _id + (_id << 8), \ 323 .dma_ch = (28 + _id), \ 324 } 325 326 #define HPBDMA_HPBIF(_id) \ 327 { \ 328 .id = HPBDMA_SLAVE_HPBIF## _id ##_TX, \ 329 .addr = 0xffda0000 + (_id * 0x1000), \ 330 .dcr = HPB_DMAE_DCR_CT | \ 331 HPB_DMAE_DCR_DIP | \ 332 HPB_DMAE_DCR_SPDS_32BIT | \ 333 HPB_DMAE_DCR_DMDL | \ 334 HPB_DMAE_DCR_DPDS_32BIT, \ 335 .port = 0x1111, \ 336 .dma_ch = (28 + _id), \ 337 }, { \ 338 .id = HPBDMA_SLAVE_HPBIF## _id ##_RX, \ 339 .addr = 0xffda0000 + (_id * 0x1000), \ 340 .dcr = HPB_DMAE_DCR_CT | \ 341 HPB_DMAE_DCR_DIP | \ 342 HPB_DMAE_DCR_SMDL | \ 343 HPB_DMAE_DCR_SPDS_32BIT | \ 344 HPB_DMAE_DCR_DPDS_32BIT, \ 345 .port = 0x1111, \ 346 .dma_ch = (28 + _id), \ 347 } 348 349 static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = { 350 { 351 .id = HPBDMA_SLAVE_SDHI0_TX, 352 .addr = 0xffe4c000 + 0x30, 353 .dcr = HPB_DMAE_DCR_SPDS_16BIT | 354 HPB_DMAE_DCR_DMDL | 355 HPB_DMAE_DCR_DPDS_16BIT, 356 .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | 357 HPB_DMAE_ASYNCRSTR_ASRST22 | 358 HPB_DMAE_ASYNCRSTR_ASRST23, 359 .mdr = HPB_DMAE_ASYNCMDR_ASMD21_MULTI, 360 .mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK, 361 .port = 0x0D0C, 362 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, 363 .dma_ch = 21, 364 }, { 365 .id = HPBDMA_SLAVE_SDHI0_RX, 366 .addr = 0xffe4c000 + 0x30, 367 .dcr = HPB_DMAE_DCR_SMDL | 368 HPB_DMAE_DCR_SPDS_16BIT | 369 HPB_DMAE_DCR_DPDS_16BIT, 370 .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | 371 HPB_DMAE_ASYNCRSTR_ASRST22 | 372 HPB_DMAE_ASYNCRSTR_ASRST23, 373 .mdr = HPB_DMAE_ASYNCMDR_ASMD22_MULTI, 374 .mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK, 375 .port = 0x0D0C, 376 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, 377 .dma_ch = 22, 378 }, { 379 .id = HPBDMA_SLAVE_USBFUNC_TX, /* for D0 */ 380 .addr = 0xffe60018, 381 .dcr = HPB_DMAE_DCR_SPDS_32BIT | 382 HPB_DMAE_DCR_DMDL | 383 HPB_DMAE_DCR_DPDS_32BIT, 384 .port = 0x0000, 385 .dma_ch = 14, 386 }, { 387 .id = HPBDMA_SLAVE_USBFUNC_RX, /* for D1 */ 388 .addr = 0xffe6001c, 389 .dcr = HPB_DMAE_DCR_SMDL | 390 HPB_DMAE_DCR_SPDS_32BIT | 391 HPB_DMAE_DCR_DPDS_32BIT, 392 .port = 0x0101, 393 .dma_ch = 15, 394 }, 395 396 HPBDMA_SSI(0), 397 HPBDMA_SSI(1), 398 HPBDMA_SSI(2), 399 HPBDMA_SSI(3), 400 HPBDMA_SSI(4), 401 HPBDMA_SSI(5), 402 HPBDMA_SSI(6), 403 HPBDMA_SSI(7), 404 HPBDMA_SSI(8), 405 406 HPBDMA_HPBIF(0), 407 HPBDMA_HPBIF(1), 408 HPBDMA_HPBIF(2), 409 HPBDMA_HPBIF(3), 410 HPBDMA_HPBIF(4), 411 HPBDMA_HPBIF(5), 412 HPBDMA_HPBIF(6), 413 HPBDMA_HPBIF(7), 414 HPBDMA_HPBIF(8), 415 }; 416 417 static const struct hpb_dmae_channel hpb_dmae_channels[] = { 418 HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_TX), /* ch. 14 */ 419 HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_RX), /* ch. 15 */ 420 HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */ 421 HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */ 422 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_TX), /* ch. 28 */ 423 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_RX), /* ch. 28 */ 424 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_TX), /* ch. 28 */ 425 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_RX), /* ch. 28 */ 426 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_TX), /* ch. 29 */ 427 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_RX), /* ch. 29 */ 428 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_TX), /* ch. 29 */ 429 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_RX), /* ch. 29 */ 430 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_TX), /* ch. 30 */ 431 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_RX), /* ch. 30 */ 432 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_TX), /* ch. 30 */ 433 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_RX), /* ch. 30 */ 434 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_TX), /* ch. 31 */ 435 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_RX), /* ch. 31 */ 436 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_TX), /* ch. 31 */ 437 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_RX), /* ch. 31 */ 438 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_TX), /* ch. 32 */ 439 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_RX), /* ch. 32 */ 440 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_TX), /* ch. 32 */ 441 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_RX), /* ch. 32 */ 442 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_TX), /* ch. 33 */ 443 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_RX), /* ch. 33 */ 444 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_TX), /* ch. 33 */ 445 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_RX), /* ch. 33 */ 446 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_TX), /* ch. 34 */ 447 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_RX), /* ch. 34 */ 448 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_TX), /* ch. 34 */ 449 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_RX), /* ch. 34 */ 450 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_TX), /* ch. 35 */ 451 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_RX), /* ch. 35 */ 452 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_TX), /* ch. 35 */ 453 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_RX), /* ch. 35 */ 454 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_TX), /* ch. 36 */ 455 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_RX), /* ch. 36 */ 456 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_TX), /* ch. 36 */ 457 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_RX), /* ch. 36 */ 458 }; 459 460 static struct hpb_dmae_pdata dma_platform_data __initdata = { 461 .slaves = hpb_dmae_slaves, 462 .num_slaves = ARRAY_SIZE(hpb_dmae_slaves), 463 .channels = hpb_dmae_channels, 464 .num_channels = ARRAY_SIZE(hpb_dmae_channels), 465 .ts_shift = { 466 [XMIT_SZ_8BIT] = 0, 467 [XMIT_SZ_16BIT] = 1, 468 [XMIT_SZ_32BIT] = 2, 469 }, 470 .num_hw_channels = 39, 471 }; 472 473 static struct resource hpb_dmae_resources[] __initdata = { 474 /* Channel registers */ 475 DEFINE_RES_MEM(0xffc08000, 0x1000), 476 /* Common registers */ 477 DEFINE_RES_MEM(0xffc09000, 0x170), 478 /* Asynchronous reset registers */ 479 DEFINE_RES_MEM(0xffc00300, 4), 480 /* Asynchronous mode registers */ 481 DEFINE_RES_MEM(0xffc00400, 4), 482 /* IRQ for DMA channels */ 483 DEFINE_RES_NAMED(gic_iid(0x7b), 5, NULL, IORESOURCE_IRQ), 484 }; 485 486 static void __init r8a7778_register_hpb_dmae(void) 487 { 488 platform_device_register_resndata(NULL, "hpb-dma-engine", 489 -1, hpb_dmae_resources, 490 ARRAY_SIZE(hpb_dmae_resources), 491 &dma_platform_data, 492 sizeof(dma_platform_data)); 493 } 494 495 void __init r8a7778_add_standard_devices(void) 496 { 497 r8a7778_add_dt_devices(); 498 r8a7778_register_tmu(0); 499 r8a7778_register_scif(0); 500 r8a7778_register_scif(1); 501 r8a7778_register_scif(2); 502 r8a7778_register_scif(3); 503 r8a7778_register_scif(4); 504 r8a7778_register_scif(5); 505 r8a7778_register_i2c(0); 506 r8a7778_register_i2c(1); 507 r8a7778_register_i2c(2); 508 r8a7778_register_i2c(3); 509 r8a7778_register_hspi(0); 510 r8a7778_register_hspi(1); 511 r8a7778_register_hspi(2); 512 513 r8a7778_register_hpb_dmae(); 514 } 515 516 void __init r8a7778_init_late(void) 517 { 518 shmobile_init_late(); 519 platform_device_register_full(&ehci_info); 520 platform_device_register_full(&ohci_info); 521 } 522 523 static struct renesas_intc_irqpin_config irqpin_platform_data __initdata = { 524 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ 525 .sense_bitfield_width = 2, 526 }; 527 528 static struct resource irqpin_resources[] __initdata = { 529 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ 530 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ 531 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ 532 DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ 533 DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ 534 DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */ 535 DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */ 536 DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */ 537 DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */ 538 }; 539 540 void __init r8a7778_init_irq_extpin_dt(int irlm) 541 { 542 void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); 543 unsigned long tmp; 544 545 if (!icr0) { 546 pr_warn("r8a7778: unable to setup external irq pin mode\n"); 547 return; 548 } 549 550 tmp = ioread32(icr0); 551 if (irlm) 552 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ 553 else 554 tmp &= ~(1 << 23); /* IRL mode - not supported */ 555 tmp |= (1 << 21); /* LVLMODE = 1 */ 556 iowrite32(tmp, icr0); 557 iounmap(icr0); 558 } 559 560 void __init r8a7778_init_irq_extpin(int irlm) 561 { 562 r8a7778_init_irq_extpin_dt(irlm); 563 if (irlm) 564 platform_device_register_resndata( 565 NULL, "renesas_intc_irqpin", -1, 566 irqpin_resources, ARRAY_SIZE(irqpin_resources), 567 &irqpin_platform_data, sizeof(irqpin_platform_data)); 568 } 569 570 void __init r8a7778_init_delay(void) 571 { 572 shmobile_init_delay(); 573 } 574 575 #ifdef CONFIG_USE_OF 576 #define INT2SMSKCR0 0x82288 /* 0xfe782288 */ 577 #define INT2SMSKCR1 0x8228c /* 0xfe78228c */ 578 579 #define INT2NTSR0 0x00018 /* 0xfe700018 */ 580 #define INT2NTSR1 0x0002c /* 0xfe70002c */ 581 void __init r8a7778_init_irq_dt(void) 582 { 583 void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000); 584 585 BUG_ON(!base); 586 587 irqchip_init(); 588 589 /* route all interrupts to ARM */ 590 __raw_writel(0x73ffffff, base + INT2NTSR0); 591 __raw_writel(0xffffffff, base + INT2NTSR1); 592 593 /* unmask all known interrupts in INTCS2 */ 594 __raw_writel(0x08330773, base + INT2SMSKCR0); 595 __raw_writel(0x00311110, base + INT2SMSKCR1); 596 597 iounmap(base); 598 } 599 600 static const char *r8a7778_compat_dt[] __initdata = { 601 "renesas,r8a7778", 602 NULL, 603 }; 604 605 DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") 606 .init_early = r8a7778_init_delay, 607 .init_irq = r8a7778_init_irq_dt, 608 .init_late = shmobile_init_late, 609 .dt_compat = r8a7778_compat_dt, 610 MACHINE_END 611 612 #endif /* CONFIG_USE_OF */ 613