1ccb7cc74SKuninori Morimoto /* 2ccb7cc74SKuninori Morimoto * r8a7778 processor support 3ccb7cc74SKuninori Morimoto * 4ccb7cc74SKuninori Morimoto * Copyright (C) 2013 Renesas Solutions Corp. 5ccb7cc74SKuninori Morimoto * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6ccb7cc74SKuninori Morimoto * 7ccb7cc74SKuninori Morimoto * This program is free software; you can redistribute it and/or modify 8ccb7cc74SKuninori Morimoto * it under the terms of the GNU General Public License as published by 9ccb7cc74SKuninori Morimoto * the Free Software Foundation; version 2 of the License. 10ccb7cc74SKuninori Morimoto * 11ccb7cc74SKuninori Morimoto * This program is distributed in the hope that it will be useful, 12ccb7cc74SKuninori Morimoto * but WITHOUT ANY WARRANTY; without even the implied warranty of 13ccb7cc74SKuninori Morimoto * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14ccb7cc74SKuninori Morimoto * GNU General Public License for more details. 15ccb7cc74SKuninori Morimoto * 16ccb7cc74SKuninori Morimoto * You should have received a copy of the GNU General Public License 17ccb7cc74SKuninori Morimoto * along with this program; if not, write to the Free Software 18ccb7cc74SKuninori Morimoto * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19ccb7cc74SKuninori Morimoto */ 20ccb7cc74SKuninori Morimoto 21ccb7cc74SKuninori Morimoto #include <linux/kernel.h> 22ccb7cc74SKuninori Morimoto #include <linux/io.h> 23ccb7cc74SKuninori Morimoto #include <linux/irqchip/arm-gic.h> 24ccb7cc74SKuninori Morimoto #include <linux/of.h> 25ccb7cc74SKuninori Morimoto #include <linux/of_platform.h> 26ccb7cc74SKuninori Morimoto #include <linux/platform_device.h> 27ccb7cc74SKuninori Morimoto #include <linux/irqchip.h> 28db331fc8SKuninori Morimoto #include <linux/serial_sci.h> 29ccb7cc74SKuninori Morimoto #include <linux/sh_timer.h> 30ccb7cc74SKuninori Morimoto #include <mach/irqs.h> 31ccb7cc74SKuninori Morimoto #include <mach/r8a7778.h> 32ccb7cc74SKuninori Morimoto #include <mach/common.h> 33ccb7cc74SKuninori Morimoto #include <asm/mach/arch.h> 34ccb7cc74SKuninori Morimoto #include <asm/hardware/cache-l2x0.h> 35ccb7cc74SKuninori Morimoto 36db331fc8SKuninori Morimoto /* SCIF */ 37db331fc8SKuninori Morimoto #define SCIF_INFO(baseaddr, irq) \ 38db331fc8SKuninori Morimoto { \ 39db331fc8SKuninori Morimoto .mapbase = baseaddr, \ 40db331fc8SKuninori Morimoto .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 41db331fc8SKuninori Morimoto .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ 42db331fc8SKuninori Morimoto .scbrr_algo_id = SCBRR_ALGO_2, \ 43db331fc8SKuninori Morimoto .type = PORT_SCIF, \ 44db331fc8SKuninori Morimoto .irqs = SCIx_IRQ_MUXED(irq), \ 45db331fc8SKuninori Morimoto } 46db331fc8SKuninori Morimoto 47db331fc8SKuninori Morimoto static struct plat_sci_port scif_platform_data[] = { 48db331fc8SKuninori Morimoto SCIF_INFO(0xffe40000, gic_iid(0x66)), 49db331fc8SKuninori Morimoto SCIF_INFO(0xffe41000, gic_iid(0x67)), 50db331fc8SKuninori Morimoto SCIF_INFO(0xffe42000, gic_iid(0x68)), 51db331fc8SKuninori Morimoto SCIF_INFO(0xffe43000, gic_iid(0x69)), 52db331fc8SKuninori Morimoto SCIF_INFO(0xffe44000, gic_iid(0x6a)), 53db331fc8SKuninori Morimoto SCIF_INFO(0xffe45000, gic_iid(0x6b)), 54db331fc8SKuninori Morimoto }; 55db331fc8SKuninori Morimoto 56ccb7cc74SKuninori Morimoto /* TMU */ 57ccb7cc74SKuninori Morimoto static struct resource sh_tmu0_resources[] = { 58ccb7cc74SKuninori Morimoto DEFINE_RES_MEM(0xffd80008, 12), 59ccb7cc74SKuninori Morimoto DEFINE_RES_IRQ(gic_iid(0x40)), 60ccb7cc74SKuninori Morimoto }; 61ccb7cc74SKuninori Morimoto 62ccb7cc74SKuninori Morimoto static struct sh_timer_config sh_tmu0_platform_data = { 63ccb7cc74SKuninori Morimoto .name = "TMU00", 64ccb7cc74SKuninori Morimoto .channel_offset = 0x4, 65ccb7cc74SKuninori Morimoto .timer_bit = 0, 66ccb7cc74SKuninori Morimoto .clockevent_rating = 200, 67ccb7cc74SKuninori Morimoto }; 68ccb7cc74SKuninori Morimoto 69ccb7cc74SKuninori Morimoto static struct resource sh_tmu1_resources[] = { 70ccb7cc74SKuninori Morimoto DEFINE_RES_MEM(0xffd80014, 12), 71ccb7cc74SKuninori Morimoto DEFINE_RES_IRQ(gic_iid(0x41)), 72ccb7cc74SKuninori Morimoto }; 73ccb7cc74SKuninori Morimoto 74ccb7cc74SKuninori Morimoto static struct sh_timer_config sh_tmu1_platform_data = { 75ccb7cc74SKuninori Morimoto .name = "TMU01", 76ccb7cc74SKuninori Morimoto .channel_offset = 0x10, 77ccb7cc74SKuninori Morimoto .timer_bit = 1, 78ccb7cc74SKuninori Morimoto .clocksource_rating = 200, 79ccb7cc74SKuninori Morimoto }; 80ccb7cc74SKuninori Morimoto 8181484487SKuninori Morimoto #define r8a7778_register_tmu(idx) \ 8281484487SKuninori Morimoto platform_device_register_resndata( \ 8381484487SKuninori Morimoto &platform_bus, "sh_tmu", idx, \ 8481484487SKuninori Morimoto sh_tmu##idx##_resources, \ 8581484487SKuninori Morimoto ARRAY_SIZE(sh_tmu##idx##_resources), \ 8681484487SKuninori Morimoto &sh_tmu##idx##_platform_data, \ 8781484487SKuninori Morimoto sizeof(sh_tmu##idx##_platform_data)) 88ccb7cc74SKuninori Morimoto 89ccb7cc74SKuninori Morimoto void __init r8a7778_add_standard_devices(void) 90ccb7cc74SKuninori Morimoto { 91ccb7cc74SKuninori Morimoto int i; 92ccb7cc74SKuninori Morimoto 93ccb7cc74SKuninori Morimoto #ifdef CONFIG_CACHE_L2X0 94ccb7cc74SKuninori Morimoto void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); 95ccb7cc74SKuninori Morimoto if (base) { 96ccb7cc74SKuninori Morimoto /* 97ccb7cc74SKuninori Morimoto * Early BRESP enable, Shared attribute override enable, 64K*16way 98ccb7cc74SKuninori Morimoto * don't call iounmap(base) 99ccb7cc74SKuninori Morimoto */ 100ccb7cc74SKuninori Morimoto l2x0_init(base, 0x40470000, 0x82000fff); 101ccb7cc74SKuninori Morimoto } 102ccb7cc74SKuninori Morimoto #endif 103ccb7cc74SKuninori Morimoto 104db331fc8SKuninori Morimoto for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++) 105db331fc8SKuninori Morimoto platform_device_register_data(&platform_bus, "sh-sci", i, 106db331fc8SKuninori Morimoto &scif_platform_data[i], 107db331fc8SKuninori Morimoto sizeof(struct plat_sci_port)); 108db331fc8SKuninori Morimoto 10981484487SKuninori Morimoto r8a7778_register_tmu(0); 11081484487SKuninori Morimoto r8a7778_register_tmu(1); 111ccb7cc74SKuninori Morimoto } 112ccb7cc74SKuninori Morimoto 113ccb7cc74SKuninori Morimoto #define INT2SMSKCR0 0x82288 /* 0xfe782288 */ 114ccb7cc74SKuninori Morimoto #define INT2SMSKCR1 0x8228c /* 0xfe78228c */ 115ccb7cc74SKuninori Morimoto 116ccb7cc74SKuninori Morimoto #define INT2NTSR0 0x00018 /* 0xfe700018 */ 117ccb7cc74SKuninori Morimoto #define INT2NTSR1 0x0002c /* 0xfe70002c */ 118ccb7cc74SKuninori Morimoto static void __init r8a7778_init_irq_common(void) 119ccb7cc74SKuninori Morimoto { 120ccb7cc74SKuninori Morimoto void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000); 121ccb7cc74SKuninori Morimoto 122ccb7cc74SKuninori Morimoto BUG_ON(!base); 123ccb7cc74SKuninori Morimoto 124ccb7cc74SKuninori Morimoto /* route all interrupts to ARM */ 125ccb7cc74SKuninori Morimoto __raw_writel(0x73ffffff, base + INT2NTSR0); 126ccb7cc74SKuninori Morimoto __raw_writel(0xffffffff, base + INT2NTSR1); 127ccb7cc74SKuninori Morimoto 128ccb7cc74SKuninori Morimoto /* unmask all known interrupts in INTCS2 */ 129ccb7cc74SKuninori Morimoto __raw_writel(0x08330773, base + INT2SMSKCR0); 130ccb7cc74SKuninori Morimoto __raw_writel(0x00311110, base + INT2SMSKCR1); 131ccb7cc74SKuninori Morimoto 132ccb7cc74SKuninori Morimoto iounmap(base); 133ccb7cc74SKuninori Morimoto } 134ccb7cc74SKuninori Morimoto 135ccb7cc74SKuninori Morimoto void __init r8a7778_init_irq(void) 136ccb7cc74SKuninori Morimoto { 137ccb7cc74SKuninori Morimoto void __iomem *gic_dist_base; 138ccb7cc74SKuninori Morimoto void __iomem *gic_cpu_base; 139ccb7cc74SKuninori Morimoto 140ccb7cc74SKuninori Morimoto gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE); 141ccb7cc74SKuninori Morimoto gic_cpu_base = ioremap_nocache(0xfe430000, PAGE_SIZE); 142ccb7cc74SKuninori Morimoto BUG_ON(!gic_dist_base || !gic_cpu_base); 143ccb7cc74SKuninori Morimoto 144ccb7cc74SKuninori Morimoto /* use GIC to handle interrupts */ 145ccb7cc74SKuninori Morimoto gic_init(0, 29, gic_dist_base, gic_cpu_base); 146ccb7cc74SKuninori Morimoto 147ccb7cc74SKuninori Morimoto r8a7778_init_irq_common(); 148ccb7cc74SKuninori Morimoto } 149ccb7cc74SKuninori Morimoto 150ccb7cc74SKuninori Morimoto void __init r8a7778_init_delay(void) 151ccb7cc74SKuninori Morimoto { 152ccb7cc74SKuninori Morimoto shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ 153ccb7cc74SKuninori Morimoto } 154ccb7cc74SKuninori Morimoto 155ccb7cc74SKuninori Morimoto #ifdef CONFIG_USE_OF 156ccb7cc74SKuninori Morimoto void __init r8a7778_init_irq_dt(void) 157ccb7cc74SKuninori Morimoto { 158ccb7cc74SKuninori Morimoto irqchip_init(); 159ccb7cc74SKuninori Morimoto r8a7778_init_irq_common(); 160ccb7cc74SKuninori Morimoto } 161ccb7cc74SKuninori Morimoto 162ccb7cc74SKuninori Morimoto static const struct of_dev_auxdata r8a7778_auxdata_lookup[] __initconst = { 163ccb7cc74SKuninori Morimoto {}, 164ccb7cc74SKuninori Morimoto }; 165ccb7cc74SKuninori Morimoto 166ccb7cc74SKuninori Morimoto void __init r8a7778_add_standard_devices_dt(void) 167ccb7cc74SKuninori Morimoto { 168ccb7cc74SKuninori Morimoto of_platform_populate(NULL, of_default_bus_match_table, 169ccb7cc74SKuninori Morimoto r8a7778_auxdata_lookup, NULL); 170ccb7cc74SKuninori Morimoto } 171ccb7cc74SKuninori Morimoto 172ccb7cc74SKuninori Morimoto static const char *r8a7778_compat_dt[] __initdata = { 173ccb7cc74SKuninori Morimoto "renesas,r8a7778", 174ccb7cc74SKuninori Morimoto NULL, 175ccb7cc74SKuninori Morimoto }; 176ccb7cc74SKuninori Morimoto 177ccb7cc74SKuninori Morimoto DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") 178ccb7cc74SKuninori Morimoto .init_early = r8a7778_init_delay, 179ccb7cc74SKuninori Morimoto .init_irq = r8a7778_init_irq_dt, 180ccb7cc74SKuninori Morimoto .init_machine = r8a7778_add_standard_devices_dt, 181ccb7cc74SKuninori Morimoto .init_time = shmobile_timer_init, 182ccb7cc74SKuninori Morimoto .dt_compat = r8a7778_compat_dt, 183ccb7cc74SKuninori Morimoto MACHINE_END 184ccb7cc74SKuninori Morimoto 185ccb7cc74SKuninori Morimoto #endif /* CONFIG_USE_OF */ 186