1ccb7cc74SKuninori Morimoto /* 2ccb7cc74SKuninori Morimoto * r8a7778 processor support 3ccb7cc74SKuninori Morimoto * 4ccb7cc74SKuninori Morimoto * Copyright (C) 2013 Renesas Solutions Corp. 5ccb7cc74SKuninori Morimoto * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6ccb7cc74SKuninori Morimoto * 7ccb7cc74SKuninori Morimoto * This program is free software; you can redistribute it and/or modify 8ccb7cc74SKuninori Morimoto * it under the terms of the GNU General Public License as published by 9ccb7cc74SKuninori Morimoto * the Free Software Foundation; version 2 of the License. 10ccb7cc74SKuninori Morimoto * 11ccb7cc74SKuninori Morimoto * This program is distributed in the hope that it will be useful, 12ccb7cc74SKuninori Morimoto * but WITHOUT ANY WARRANTY; without even the implied warranty of 13ccb7cc74SKuninori Morimoto * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14ccb7cc74SKuninori Morimoto * GNU General Public License for more details. 15ccb7cc74SKuninori Morimoto * 16ccb7cc74SKuninori Morimoto * You should have received a copy of the GNU General Public License 17ccb7cc74SKuninori Morimoto * along with this program; if not, write to the Free Software 18ccb7cc74SKuninori Morimoto * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19ccb7cc74SKuninori Morimoto */ 20ccb7cc74SKuninori Morimoto 21ccb7cc74SKuninori Morimoto #include <linux/kernel.h> 22ccb7cc74SKuninori Morimoto #include <linux/io.h> 23ccb7cc74SKuninori Morimoto #include <linux/irqchip/arm-gic.h> 24ccb7cc74SKuninori Morimoto #include <linux/of.h> 25ccb7cc74SKuninori Morimoto #include <linux/of_platform.h> 263a42fa20SKuninori Morimoto #include <linux/platform_data/irq-renesas-intc-irqpin.h> 27ccb7cc74SKuninori Morimoto #include <linux/platform_device.h> 28ccb7cc74SKuninori Morimoto #include <linux/irqchip.h> 29db331fc8SKuninori Morimoto #include <linux/serial_sci.h> 30ccb7cc74SKuninori Morimoto #include <linux/sh_timer.h> 31ccb7cc74SKuninori Morimoto #include <mach/irqs.h> 32ccb7cc74SKuninori Morimoto #include <mach/r8a7778.h> 33ccb7cc74SKuninori Morimoto #include <mach/common.h> 34ccb7cc74SKuninori Morimoto #include <asm/mach/arch.h> 35ccb7cc74SKuninori Morimoto #include <asm/hardware/cache-l2x0.h> 36ccb7cc74SKuninori Morimoto 37db331fc8SKuninori Morimoto /* SCIF */ 38db331fc8SKuninori Morimoto #define SCIF_INFO(baseaddr, irq) \ 39db331fc8SKuninori Morimoto { \ 40db331fc8SKuninori Morimoto .mapbase = baseaddr, \ 41db331fc8SKuninori Morimoto .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 42db331fc8SKuninori Morimoto .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ 43db331fc8SKuninori Morimoto .scbrr_algo_id = SCBRR_ALGO_2, \ 44db331fc8SKuninori Morimoto .type = PORT_SCIF, \ 45db331fc8SKuninori Morimoto .irqs = SCIx_IRQ_MUXED(irq), \ 46db331fc8SKuninori Morimoto } 47db331fc8SKuninori Morimoto 48db331fc8SKuninori Morimoto static struct plat_sci_port scif_platform_data[] = { 49db331fc8SKuninori Morimoto SCIF_INFO(0xffe40000, gic_iid(0x66)), 50db331fc8SKuninori Morimoto SCIF_INFO(0xffe41000, gic_iid(0x67)), 51db331fc8SKuninori Morimoto SCIF_INFO(0xffe42000, gic_iid(0x68)), 52db331fc8SKuninori Morimoto SCIF_INFO(0xffe43000, gic_iid(0x69)), 53db331fc8SKuninori Morimoto SCIF_INFO(0xffe44000, gic_iid(0x6a)), 54db331fc8SKuninori Morimoto SCIF_INFO(0xffe45000, gic_iid(0x6b)), 55db331fc8SKuninori Morimoto }; 56db331fc8SKuninori Morimoto 57ccb7cc74SKuninori Morimoto /* TMU */ 58ccb7cc74SKuninori Morimoto static struct resource sh_tmu0_resources[] = { 59ccb7cc74SKuninori Morimoto DEFINE_RES_MEM(0xffd80008, 12), 60ccb7cc74SKuninori Morimoto DEFINE_RES_IRQ(gic_iid(0x40)), 61ccb7cc74SKuninori Morimoto }; 62ccb7cc74SKuninori Morimoto 63ccb7cc74SKuninori Morimoto static struct sh_timer_config sh_tmu0_platform_data = { 64ccb7cc74SKuninori Morimoto .name = "TMU00", 65ccb7cc74SKuninori Morimoto .channel_offset = 0x4, 66ccb7cc74SKuninori Morimoto .timer_bit = 0, 67ccb7cc74SKuninori Morimoto .clockevent_rating = 200, 68ccb7cc74SKuninori Morimoto }; 69ccb7cc74SKuninori Morimoto 70ccb7cc74SKuninori Morimoto static struct resource sh_tmu1_resources[] = { 71ccb7cc74SKuninori Morimoto DEFINE_RES_MEM(0xffd80014, 12), 72ccb7cc74SKuninori Morimoto DEFINE_RES_IRQ(gic_iid(0x41)), 73ccb7cc74SKuninori Morimoto }; 74ccb7cc74SKuninori Morimoto 75ccb7cc74SKuninori Morimoto static struct sh_timer_config sh_tmu1_platform_data = { 76ccb7cc74SKuninori Morimoto .name = "TMU01", 77ccb7cc74SKuninori Morimoto .channel_offset = 0x10, 78ccb7cc74SKuninori Morimoto .timer_bit = 1, 79ccb7cc74SKuninori Morimoto .clocksource_rating = 200, 80ccb7cc74SKuninori Morimoto }; 81ccb7cc74SKuninori Morimoto 8281484487SKuninori Morimoto #define r8a7778_register_tmu(idx) \ 8381484487SKuninori Morimoto platform_device_register_resndata( \ 8481484487SKuninori Morimoto &platform_bus, "sh_tmu", idx, \ 8581484487SKuninori Morimoto sh_tmu##idx##_resources, \ 8681484487SKuninori Morimoto ARRAY_SIZE(sh_tmu##idx##_resources), \ 8781484487SKuninori Morimoto &sh_tmu##idx##_platform_data, \ 8881484487SKuninori Morimoto sizeof(sh_tmu##idx##_platform_data)) 89ccb7cc74SKuninori Morimoto 90ccb7cc74SKuninori Morimoto void __init r8a7778_add_standard_devices(void) 91ccb7cc74SKuninori Morimoto { 92ccb7cc74SKuninori Morimoto int i; 93ccb7cc74SKuninori Morimoto 94ccb7cc74SKuninori Morimoto #ifdef CONFIG_CACHE_L2X0 95ccb7cc74SKuninori Morimoto void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); 96ccb7cc74SKuninori Morimoto if (base) { 97ccb7cc74SKuninori Morimoto /* 98ccb7cc74SKuninori Morimoto * Early BRESP enable, Shared attribute override enable, 64K*16way 99ccb7cc74SKuninori Morimoto * don't call iounmap(base) 100ccb7cc74SKuninori Morimoto */ 101ccb7cc74SKuninori Morimoto l2x0_init(base, 0x40470000, 0x82000fff); 102ccb7cc74SKuninori Morimoto } 103ccb7cc74SKuninori Morimoto #endif 104ccb7cc74SKuninori Morimoto 105db331fc8SKuninori Morimoto for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++) 106db331fc8SKuninori Morimoto platform_device_register_data(&platform_bus, "sh-sci", i, 107db331fc8SKuninori Morimoto &scif_platform_data[i], 108db331fc8SKuninori Morimoto sizeof(struct plat_sci_port)); 109db331fc8SKuninori Morimoto 11081484487SKuninori Morimoto r8a7778_register_tmu(0); 11181484487SKuninori Morimoto r8a7778_register_tmu(1); 112ccb7cc74SKuninori Morimoto } 113ccb7cc74SKuninori Morimoto 1143a42fa20SKuninori Morimoto static struct renesas_intc_irqpin_config irqpin_platform_data = { 1153a42fa20SKuninori Morimoto .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ 1163a42fa20SKuninori Morimoto .sense_bitfield_width = 2, 1173a42fa20SKuninori Morimoto }; 1183a42fa20SKuninori Morimoto 1193a42fa20SKuninori Morimoto static struct resource irqpin_resources[] = { 1203a42fa20SKuninori Morimoto DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ 1213a42fa20SKuninori Morimoto DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ 1223a42fa20SKuninori Morimoto DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ 1233a42fa20SKuninori Morimoto DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ 1243a42fa20SKuninori Morimoto DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ 1253a42fa20SKuninori Morimoto DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */ 1263a42fa20SKuninori Morimoto DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */ 1273a42fa20SKuninori Morimoto DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */ 1283a42fa20SKuninori Morimoto DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */ 1293a42fa20SKuninori Morimoto }; 1303a42fa20SKuninori Morimoto 1313a42fa20SKuninori Morimoto void __init r8a7778_init_irq_extpin(int irlm) 1323a42fa20SKuninori Morimoto { 1333a42fa20SKuninori Morimoto void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); 1343a42fa20SKuninori Morimoto unsigned long tmp; 1353a42fa20SKuninori Morimoto 1363a42fa20SKuninori Morimoto if (!icr0) { 1373a42fa20SKuninori Morimoto pr_warn("r8a7778: unable to setup external irq pin mode\n"); 1383a42fa20SKuninori Morimoto return; 1393a42fa20SKuninori Morimoto } 1403a42fa20SKuninori Morimoto 1413a42fa20SKuninori Morimoto tmp = ioread32(icr0); 1423a42fa20SKuninori Morimoto if (irlm) 1433a42fa20SKuninori Morimoto tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ 1443a42fa20SKuninori Morimoto else 1453a42fa20SKuninori Morimoto tmp &= ~(1 << 23); /* IRL mode - not supported */ 1463a42fa20SKuninori Morimoto tmp |= (1 << 21); /* LVLMODE = 1 */ 1473a42fa20SKuninori Morimoto iowrite32(tmp, icr0); 1483a42fa20SKuninori Morimoto iounmap(icr0); 1493a42fa20SKuninori Morimoto 1503a42fa20SKuninori Morimoto if (irlm) 1513a42fa20SKuninori Morimoto platform_device_register_resndata( 1523a42fa20SKuninori Morimoto &platform_bus, "renesas_intc_irqpin", -1, 1533a42fa20SKuninori Morimoto irqpin_resources, ARRAY_SIZE(irqpin_resources), 1543a42fa20SKuninori Morimoto &irqpin_platform_data, sizeof(irqpin_platform_data)); 1553a42fa20SKuninori Morimoto } 1563a42fa20SKuninori Morimoto 157ccb7cc74SKuninori Morimoto #define INT2SMSKCR0 0x82288 /* 0xfe782288 */ 158ccb7cc74SKuninori Morimoto #define INT2SMSKCR1 0x8228c /* 0xfe78228c */ 159ccb7cc74SKuninori Morimoto 160ccb7cc74SKuninori Morimoto #define INT2NTSR0 0x00018 /* 0xfe700018 */ 161ccb7cc74SKuninori Morimoto #define INT2NTSR1 0x0002c /* 0xfe70002c */ 162ccb7cc74SKuninori Morimoto static void __init r8a7778_init_irq_common(void) 163ccb7cc74SKuninori Morimoto { 164ccb7cc74SKuninori Morimoto void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000); 165ccb7cc74SKuninori Morimoto 166ccb7cc74SKuninori Morimoto BUG_ON(!base); 167ccb7cc74SKuninori Morimoto 168ccb7cc74SKuninori Morimoto /* route all interrupts to ARM */ 169ccb7cc74SKuninori Morimoto __raw_writel(0x73ffffff, base + INT2NTSR0); 170ccb7cc74SKuninori Morimoto __raw_writel(0xffffffff, base + INT2NTSR1); 171ccb7cc74SKuninori Morimoto 172ccb7cc74SKuninori Morimoto /* unmask all known interrupts in INTCS2 */ 173ccb7cc74SKuninori Morimoto __raw_writel(0x08330773, base + INT2SMSKCR0); 174ccb7cc74SKuninori Morimoto __raw_writel(0x00311110, base + INT2SMSKCR1); 175ccb7cc74SKuninori Morimoto 176ccb7cc74SKuninori Morimoto iounmap(base); 177ccb7cc74SKuninori Morimoto } 178ccb7cc74SKuninori Morimoto 179ccb7cc74SKuninori Morimoto void __init r8a7778_init_irq(void) 180ccb7cc74SKuninori Morimoto { 181ccb7cc74SKuninori Morimoto void __iomem *gic_dist_base; 182ccb7cc74SKuninori Morimoto void __iomem *gic_cpu_base; 183ccb7cc74SKuninori Morimoto 184ccb7cc74SKuninori Morimoto gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE); 185ccb7cc74SKuninori Morimoto gic_cpu_base = ioremap_nocache(0xfe430000, PAGE_SIZE); 186ccb7cc74SKuninori Morimoto BUG_ON(!gic_dist_base || !gic_cpu_base); 187ccb7cc74SKuninori Morimoto 188ccb7cc74SKuninori Morimoto /* use GIC to handle interrupts */ 189ccb7cc74SKuninori Morimoto gic_init(0, 29, gic_dist_base, gic_cpu_base); 190ccb7cc74SKuninori Morimoto 191ccb7cc74SKuninori Morimoto r8a7778_init_irq_common(); 192ccb7cc74SKuninori Morimoto } 193ccb7cc74SKuninori Morimoto 194ccb7cc74SKuninori Morimoto void __init r8a7778_init_delay(void) 195ccb7cc74SKuninori Morimoto { 196ccb7cc74SKuninori Morimoto shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ 197ccb7cc74SKuninori Morimoto } 198ccb7cc74SKuninori Morimoto 199ccb7cc74SKuninori Morimoto #ifdef CONFIG_USE_OF 200ccb7cc74SKuninori Morimoto void __init r8a7778_init_irq_dt(void) 201ccb7cc74SKuninori Morimoto { 202ccb7cc74SKuninori Morimoto irqchip_init(); 203ccb7cc74SKuninori Morimoto r8a7778_init_irq_common(); 204ccb7cc74SKuninori Morimoto } 205ccb7cc74SKuninori Morimoto 206ccb7cc74SKuninori Morimoto static const struct of_dev_auxdata r8a7778_auxdata_lookup[] __initconst = { 207ccb7cc74SKuninori Morimoto {}, 208ccb7cc74SKuninori Morimoto }; 209ccb7cc74SKuninori Morimoto 210ccb7cc74SKuninori Morimoto void __init r8a7778_add_standard_devices_dt(void) 211ccb7cc74SKuninori Morimoto { 212ccb7cc74SKuninori Morimoto of_platform_populate(NULL, of_default_bus_match_table, 213ccb7cc74SKuninori Morimoto r8a7778_auxdata_lookup, NULL); 214ccb7cc74SKuninori Morimoto } 215ccb7cc74SKuninori Morimoto 216ccb7cc74SKuninori Morimoto static const char *r8a7778_compat_dt[] __initdata = { 217ccb7cc74SKuninori Morimoto "renesas,r8a7778", 218ccb7cc74SKuninori Morimoto NULL, 219ccb7cc74SKuninori Morimoto }; 220ccb7cc74SKuninori Morimoto 221ccb7cc74SKuninori Morimoto DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") 222ccb7cc74SKuninori Morimoto .init_early = r8a7778_init_delay, 223ccb7cc74SKuninori Morimoto .init_irq = r8a7778_init_irq_dt, 224ccb7cc74SKuninori Morimoto .init_machine = r8a7778_add_standard_devices_dt, 225ccb7cc74SKuninori Morimoto .init_time = shmobile_timer_init, 226ccb7cc74SKuninori Morimoto .dt_compat = r8a7778_compat_dt, 227ccb7cc74SKuninori Morimoto MACHINE_END 228ccb7cc74SKuninori Morimoto 229ccb7cc74SKuninori Morimoto #endif /* CONFIG_USE_OF */ 230