1ccb7cc74SKuninori Morimoto /* 2ccb7cc74SKuninori Morimoto * r8a7778 processor support 3ccb7cc74SKuninori Morimoto * 4ccb7cc74SKuninori Morimoto * Copyright (C) 2013 Renesas Solutions Corp. 5ccb7cc74SKuninori Morimoto * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 652421914SSergei Shtylyov * Copyright (C) 2013 Cogent Embedded, Inc. 7ccb7cc74SKuninori Morimoto * 8ccb7cc74SKuninori Morimoto * This program is free software; you can redistribute it and/or modify 9ccb7cc74SKuninori Morimoto * it under the terms of the GNU General Public License as published by 10ccb7cc74SKuninori Morimoto * the Free Software Foundation; version 2 of the License. 11ccb7cc74SKuninori Morimoto * 12ccb7cc74SKuninori Morimoto * This program is distributed in the hope that it will be useful, 13ccb7cc74SKuninori Morimoto * but WITHOUT ANY WARRANTY; without even the implied warranty of 14ccb7cc74SKuninori Morimoto * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15ccb7cc74SKuninori Morimoto * GNU General Public License for more details. 16ccb7cc74SKuninori Morimoto * 17ccb7cc74SKuninori Morimoto * You should have received a copy of the GNU General Public License 18ccb7cc74SKuninori Morimoto * along with this program; if not, write to the Free Software 19ccb7cc74SKuninori Morimoto * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 20ccb7cc74SKuninori Morimoto */ 21ccb7cc74SKuninori Morimoto 22ccb7cc74SKuninori Morimoto #include <linux/kernel.h> 23ccb7cc74SKuninori Morimoto #include <linux/io.h> 24ccb7cc74SKuninori Morimoto #include <linux/irqchip/arm-gic.h> 25ccb7cc74SKuninori Morimoto #include <linux/of.h> 26ccb7cc74SKuninori Morimoto #include <linux/of_platform.h> 2739ca2283SKuninori Morimoto #include <linux/platform_data/gpio-rcar.h> 283a42fa20SKuninori Morimoto #include <linux/platform_data/irq-renesas-intc-irqpin.h> 29ccb7cc74SKuninori Morimoto #include <linux/platform_device.h> 30ccb7cc74SKuninori Morimoto #include <linux/irqchip.h> 31db331fc8SKuninori Morimoto #include <linux/serial_sci.h> 32ccb7cc74SKuninori Morimoto #include <linux/sh_timer.h> 33ccb7cc74SKuninori Morimoto #include <mach/irqs.h> 34ccb7cc74SKuninori Morimoto #include <mach/r8a7778.h> 35ccb7cc74SKuninori Morimoto #include <mach/common.h> 36ccb7cc74SKuninori Morimoto #include <asm/mach/arch.h> 37ccb7cc74SKuninori Morimoto #include <asm/hardware/cache-l2x0.h> 38ccb7cc74SKuninori Morimoto 39db331fc8SKuninori Morimoto /* SCIF */ 40db331fc8SKuninori Morimoto #define SCIF_INFO(baseaddr, irq) \ 41db331fc8SKuninori Morimoto { \ 42db331fc8SKuninori Morimoto .mapbase = baseaddr, \ 43db331fc8SKuninori Morimoto .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 44db331fc8SKuninori Morimoto .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ 45db331fc8SKuninori Morimoto .scbrr_algo_id = SCBRR_ALGO_2, \ 46db331fc8SKuninori Morimoto .type = PORT_SCIF, \ 47db331fc8SKuninori Morimoto .irqs = SCIx_IRQ_MUXED(irq), \ 48db331fc8SKuninori Morimoto } 49db331fc8SKuninori Morimoto 50db331fc8SKuninori Morimoto static struct plat_sci_port scif_platform_data[] = { 51db331fc8SKuninori Morimoto SCIF_INFO(0xffe40000, gic_iid(0x66)), 52db331fc8SKuninori Morimoto SCIF_INFO(0xffe41000, gic_iid(0x67)), 53db331fc8SKuninori Morimoto SCIF_INFO(0xffe42000, gic_iid(0x68)), 54db331fc8SKuninori Morimoto SCIF_INFO(0xffe43000, gic_iid(0x69)), 55db331fc8SKuninori Morimoto SCIF_INFO(0xffe44000, gic_iid(0x6a)), 56db331fc8SKuninori Morimoto SCIF_INFO(0xffe45000, gic_iid(0x6b)), 57db331fc8SKuninori Morimoto }; 58db331fc8SKuninori Morimoto 59ccb7cc74SKuninori Morimoto /* TMU */ 60ccb7cc74SKuninori Morimoto static struct resource sh_tmu0_resources[] = { 61ccb7cc74SKuninori Morimoto DEFINE_RES_MEM(0xffd80008, 12), 62ccb7cc74SKuninori Morimoto DEFINE_RES_IRQ(gic_iid(0x40)), 63ccb7cc74SKuninori Morimoto }; 64ccb7cc74SKuninori Morimoto 65ccb7cc74SKuninori Morimoto static struct sh_timer_config sh_tmu0_platform_data = { 66ccb7cc74SKuninori Morimoto .name = "TMU00", 67ccb7cc74SKuninori Morimoto .channel_offset = 0x4, 68ccb7cc74SKuninori Morimoto .timer_bit = 0, 69ccb7cc74SKuninori Morimoto .clockevent_rating = 200, 70ccb7cc74SKuninori Morimoto }; 71ccb7cc74SKuninori Morimoto 72ccb7cc74SKuninori Morimoto static struct resource sh_tmu1_resources[] = { 73ccb7cc74SKuninori Morimoto DEFINE_RES_MEM(0xffd80014, 12), 74ccb7cc74SKuninori Morimoto DEFINE_RES_IRQ(gic_iid(0x41)), 75ccb7cc74SKuninori Morimoto }; 76ccb7cc74SKuninori Morimoto 77ccb7cc74SKuninori Morimoto static struct sh_timer_config sh_tmu1_platform_data = { 78ccb7cc74SKuninori Morimoto .name = "TMU01", 79ccb7cc74SKuninori Morimoto .channel_offset = 0x10, 80ccb7cc74SKuninori Morimoto .timer_bit = 1, 81ccb7cc74SKuninori Morimoto .clocksource_rating = 200, 82ccb7cc74SKuninori Morimoto }; 83ccb7cc74SKuninori Morimoto 8452421914SSergei Shtylyov /* Ether */ 8552421914SSergei Shtylyov static struct resource ether_resources[] = { 8652421914SSergei Shtylyov DEFINE_RES_MEM(0xfde00000, 0x400), 8752421914SSergei Shtylyov DEFINE_RES_IRQ(gic_iid(0x89)), 8852421914SSergei Shtylyov }; 8952421914SSergei Shtylyov 9081484487SKuninori Morimoto #define r8a7778_register_tmu(idx) \ 9181484487SKuninori Morimoto platform_device_register_resndata( \ 9281484487SKuninori Morimoto &platform_bus, "sh_tmu", idx, \ 9381484487SKuninori Morimoto sh_tmu##idx##_resources, \ 9481484487SKuninori Morimoto ARRAY_SIZE(sh_tmu##idx##_resources), \ 9581484487SKuninori Morimoto &sh_tmu##idx##_platform_data, \ 9681484487SKuninori Morimoto sizeof(sh_tmu##idx##_platform_data)) 97ccb7cc74SKuninori Morimoto 9839ca2283SKuninori Morimoto /* PFC/GPIO */ 99369b00bbSKuninori Morimoto static struct resource pfc_resources[] = { 100369b00bbSKuninori Morimoto DEFINE_RES_MEM(0xfffc0000, 0x118), 101369b00bbSKuninori Morimoto }; 102369b00bbSKuninori Morimoto 10339ca2283SKuninori Morimoto #define R8A7778_GPIO(idx) \ 10439ca2283SKuninori Morimoto static struct resource r8a7778_gpio##idx##_resources[] = { \ 10539ca2283SKuninori Morimoto DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30), \ 10639ca2283SKuninori Morimoto DEFINE_RES_IRQ(gic_iid(0x87)), \ 10739ca2283SKuninori Morimoto }; \ 10839ca2283SKuninori Morimoto \ 10939ca2283SKuninori Morimoto static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data = { \ 11039ca2283SKuninori Morimoto .gpio_base = 32 * (idx), \ 11139ca2283SKuninori Morimoto .irq_base = GPIO_IRQ_BASE(idx), \ 11239ca2283SKuninori Morimoto .number_of_pins = 32, \ 11339ca2283SKuninori Morimoto .pctl_name = "pfc-r8a7778", \ 11439ca2283SKuninori Morimoto } 11539ca2283SKuninori Morimoto 11639ca2283SKuninori Morimoto R8A7778_GPIO(0); 11739ca2283SKuninori Morimoto R8A7778_GPIO(1); 11839ca2283SKuninori Morimoto R8A7778_GPIO(2); 11939ca2283SKuninori Morimoto R8A7778_GPIO(3); 12039ca2283SKuninori Morimoto R8A7778_GPIO(4); 12139ca2283SKuninori Morimoto 12239ca2283SKuninori Morimoto #define r8a7778_register_gpio(idx) \ 12339ca2283SKuninori Morimoto platform_device_register_resndata( \ 12439ca2283SKuninori Morimoto &platform_bus, "gpio_rcar", idx, \ 12539ca2283SKuninori Morimoto r8a7778_gpio##idx##_resources, \ 12639ca2283SKuninori Morimoto ARRAY_SIZE(r8a7778_gpio##idx##_resources), \ 12739ca2283SKuninori Morimoto &r8a7778_gpio##idx##_platform_data, \ 12839ca2283SKuninori Morimoto sizeof(r8a7778_gpio##idx##_platform_data)) 12939ca2283SKuninori Morimoto 130369b00bbSKuninori Morimoto void __init r8a7778_pinmux_init(void) 131369b00bbSKuninori Morimoto { 132369b00bbSKuninori Morimoto platform_device_register_simple( 133369b00bbSKuninori Morimoto "pfc-r8a7778", -1, 134369b00bbSKuninori Morimoto pfc_resources, 135369b00bbSKuninori Morimoto ARRAY_SIZE(pfc_resources)); 13639ca2283SKuninori Morimoto 13739ca2283SKuninori Morimoto r8a7778_register_gpio(0); 13839ca2283SKuninori Morimoto r8a7778_register_gpio(1); 13939ca2283SKuninori Morimoto r8a7778_register_gpio(2); 14039ca2283SKuninori Morimoto r8a7778_register_gpio(3); 14139ca2283SKuninori Morimoto r8a7778_register_gpio(4); 142369b00bbSKuninori Morimoto } 143369b00bbSKuninori Morimoto 144ccb7cc74SKuninori Morimoto void __init r8a7778_add_standard_devices(void) 145ccb7cc74SKuninori Morimoto { 146ccb7cc74SKuninori Morimoto int i; 147ccb7cc74SKuninori Morimoto 148ccb7cc74SKuninori Morimoto #ifdef CONFIG_CACHE_L2X0 149ccb7cc74SKuninori Morimoto void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); 150ccb7cc74SKuninori Morimoto if (base) { 151ccb7cc74SKuninori Morimoto /* 152ccb7cc74SKuninori Morimoto * Early BRESP enable, Shared attribute override enable, 64K*16way 153ccb7cc74SKuninori Morimoto * don't call iounmap(base) 154ccb7cc74SKuninori Morimoto */ 155ccb7cc74SKuninori Morimoto l2x0_init(base, 0x40470000, 0x82000fff); 156ccb7cc74SKuninori Morimoto } 157ccb7cc74SKuninori Morimoto #endif 158ccb7cc74SKuninori Morimoto 159db331fc8SKuninori Morimoto for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++) 160db331fc8SKuninori Morimoto platform_device_register_data(&platform_bus, "sh-sci", i, 161db331fc8SKuninori Morimoto &scif_platform_data[i], 162db331fc8SKuninori Morimoto sizeof(struct plat_sci_port)); 163db331fc8SKuninori Morimoto 16481484487SKuninori Morimoto r8a7778_register_tmu(0); 16581484487SKuninori Morimoto r8a7778_register_tmu(1); 166ccb7cc74SKuninori Morimoto } 167ccb7cc74SKuninori Morimoto 16852421914SSergei Shtylyov void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata) 16952421914SSergei Shtylyov { 17052421914SSergei Shtylyov platform_device_register_resndata(&platform_bus, "sh_eth", -1, 17152421914SSergei Shtylyov ether_resources, 17252421914SSergei Shtylyov ARRAY_SIZE(ether_resources), 17352421914SSergei Shtylyov pdata, sizeof(*pdata)); 17452421914SSergei Shtylyov } 17552421914SSergei Shtylyov 1763a42fa20SKuninori Morimoto static struct renesas_intc_irqpin_config irqpin_platform_data = { 1773a42fa20SKuninori Morimoto .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ 1783a42fa20SKuninori Morimoto .sense_bitfield_width = 2, 1793a42fa20SKuninori Morimoto }; 1803a42fa20SKuninori Morimoto 1813a42fa20SKuninori Morimoto static struct resource irqpin_resources[] = { 1823a42fa20SKuninori Morimoto DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ 1833a42fa20SKuninori Morimoto DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ 1843a42fa20SKuninori Morimoto DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ 1853a42fa20SKuninori Morimoto DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ 1863a42fa20SKuninori Morimoto DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ 1873a42fa20SKuninori Morimoto DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */ 1883a42fa20SKuninori Morimoto DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */ 1893a42fa20SKuninori Morimoto DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */ 1903a42fa20SKuninori Morimoto DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */ 1913a42fa20SKuninori Morimoto }; 1923a42fa20SKuninori Morimoto 1933a42fa20SKuninori Morimoto void __init r8a7778_init_irq_extpin(int irlm) 1943a42fa20SKuninori Morimoto { 1953a42fa20SKuninori Morimoto void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); 1963a42fa20SKuninori Morimoto unsigned long tmp; 1973a42fa20SKuninori Morimoto 1983a42fa20SKuninori Morimoto if (!icr0) { 1993a42fa20SKuninori Morimoto pr_warn("r8a7778: unable to setup external irq pin mode\n"); 2003a42fa20SKuninori Morimoto return; 2013a42fa20SKuninori Morimoto } 2023a42fa20SKuninori Morimoto 2033a42fa20SKuninori Morimoto tmp = ioread32(icr0); 2043a42fa20SKuninori Morimoto if (irlm) 2053a42fa20SKuninori Morimoto tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ 2063a42fa20SKuninori Morimoto else 2073a42fa20SKuninori Morimoto tmp &= ~(1 << 23); /* IRL mode - not supported */ 2083a42fa20SKuninori Morimoto tmp |= (1 << 21); /* LVLMODE = 1 */ 2093a42fa20SKuninori Morimoto iowrite32(tmp, icr0); 2103a42fa20SKuninori Morimoto iounmap(icr0); 2113a42fa20SKuninori Morimoto 2123a42fa20SKuninori Morimoto if (irlm) 2133a42fa20SKuninori Morimoto platform_device_register_resndata( 2143a42fa20SKuninori Morimoto &platform_bus, "renesas_intc_irqpin", -1, 2153a42fa20SKuninori Morimoto irqpin_resources, ARRAY_SIZE(irqpin_resources), 2163a42fa20SKuninori Morimoto &irqpin_platform_data, sizeof(irqpin_platform_data)); 2173a42fa20SKuninori Morimoto } 2183a42fa20SKuninori Morimoto 219ccb7cc74SKuninori Morimoto #define INT2SMSKCR0 0x82288 /* 0xfe782288 */ 220ccb7cc74SKuninori Morimoto #define INT2SMSKCR1 0x8228c /* 0xfe78228c */ 221ccb7cc74SKuninori Morimoto 222ccb7cc74SKuninori Morimoto #define INT2NTSR0 0x00018 /* 0xfe700018 */ 223ccb7cc74SKuninori Morimoto #define INT2NTSR1 0x0002c /* 0xfe70002c */ 224ccb7cc74SKuninori Morimoto static void __init r8a7778_init_irq_common(void) 225ccb7cc74SKuninori Morimoto { 226ccb7cc74SKuninori Morimoto void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000); 227ccb7cc74SKuninori Morimoto 228ccb7cc74SKuninori Morimoto BUG_ON(!base); 229ccb7cc74SKuninori Morimoto 230ccb7cc74SKuninori Morimoto /* route all interrupts to ARM */ 231ccb7cc74SKuninori Morimoto __raw_writel(0x73ffffff, base + INT2NTSR0); 232ccb7cc74SKuninori Morimoto __raw_writel(0xffffffff, base + INT2NTSR1); 233ccb7cc74SKuninori Morimoto 234ccb7cc74SKuninori Morimoto /* unmask all known interrupts in INTCS2 */ 235ccb7cc74SKuninori Morimoto __raw_writel(0x08330773, base + INT2SMSKCR0); 236ccb7cc74SKuninori Morimoto __raw_writel(0x00311110, base + INT2SMSKCR1); 237ccb7cc74SKuninori Morimoto 238ccb7cc74SKuninori Morimoto iounmap(base); 239ccb7cc74SKuninori Morimoto } 240ccb7cc74SKuninori Morimoto 241ccb7cc74SKuninori Morimoto void __init r8a7778_init_irq(void) 242ccb7cc74SKuninori Morimoto { 243ccb7cc74SKuninori Morimoto void __iomem *gic_dist_base; 244ccb7cc74SKuninori Morimoto void __iomem *gic_cpu_base; 245ccb7cc74SKuninori Morimoto 246ccb7cc74SKuninori Morimoto gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE); 247ccb7cc74SKuninori Morimoto gic_cpu_base = ioremap_nocache(0xfe430000, PAGE_SIZE); 248ccb7cc74SKuninori Morimoto BUG_ON(!gic_dist_base || !gic_cpu_base); 249ccb7cc74SKuninori Morimoto 250ccb7cc74SKuninori Morimoto /* use GIC to handle interrupts */ 251ccb7cc74SKuninori Morimoto gic_init(0, 29, gic_dist_base, gic_cpu_base); 252ccb7cc74SKuninori Morimoto 253ccb7cc74SKuninori Morimoto r8a7778_init_irq_common(); 254ccb7cc74SKuninori Morimoto } 255ccb7cc74SKuninori Morimoto 256ccb7cc74SKuninori Morimoto void __init r8a7778_init_delay(void) 257ccb7cc74SKuninori Morimoto { 258ccb7cc74SKuninori Morimoto shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ 259ccb7cc74SKuninori Morimoto } 260ccb7cc74SKuninori Morimoto 261ccb7cc74SKuninori Morimoto #ifdef CONFIG_USE_OF 262ccb7cc74SKuninori Morimoto void __init r8a7778_init_irq_dt(void) 263ccb7cc74SKuninori Morimoto { 264ccb7cc74SKuninori Morimoto irqchip_init(); 265ccb7cc74SKuninori Morimoto r8a7778_init_irq_common(); 266ccb7cc74SKuninori Morimoto } 267ccb7cc74SKuninori Morimoto 268ccb7cc74SKuninori Morimoto static const struct of_dev_auxdata r8a7778_auxdata_lookup[] __initconst = { 269ccb7cc74SKuninori Morimoto {}, 270ccb7cc74SKuninori Morimoto }; 271ccb7cc74SKuninori Morimoto 272ccb7cc74SKuninori Morimoto void __init r8a7778_add_standard_devices_dt(void) 273ccb7cc74SKuninori Morimoto { 274ccb7cc74SKuninori Morimoto of_platform_populate(NULL, of_default_bus_match_table, 275ccb7cc74SKuninori Morimoto r8a7778_auxdata_lookup, NULL); 276ccb7cc74SKuninori Morimoto } 277ccb7cc74SKuninori Morimoto 278ccb7cc74SKuninori Morimoto static const char *r8a7778_compat_dt[] __initdata = { 279ccb7cc74SKuninori Morimoto "renesas,r8a7778", 280ccb7cc74SKuninori Morimoto NULL, 281ccb7cc74SKuninori Morimoto }; 282ccb7cc74SKuninori Morimoto 283ccb7cc74SKuninori Morimoto DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") 284ccb7cc74SKuninori Morimoto .init_early = r8a7778_init_delay, 285ccb7cc74SKuninori Morimoto .init_irq = r8a7778_init_irq_dt, 286ccb7cc74SKuninori Morimoto .init_machine = r8a7778_add_standard_devices_dt, 287ccb7cc74SKuninori Morimoto .init_time = shmobile_timer_init, 288ccb7cc74SKuninori Morimoto .dt_compat = r8a7778_compat_dt, 289ccb7cc74SKuninori Morimoto MACHINE_END 290ccb7cc74SKuninori Morimoto 291ccb7cc74SKuninori Morimoto #endif /* CONFIG_USE_OF */ 292