1 /*
2  * R8A7740 processor support
3  *
4  * Copyright (C) 2011  Renesas Solutions Corp.
5  * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; version 2 of the License.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  */
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/io.h>
19 #include <linux/irqchip.h>
20 #include <linux/irqchip/arm-gic.h>
21 
22 #include <asm/mach/map.h>
23 #include <asm/mach/arch.h>
24 #include <asm/mach/time.h>
25 
26 #include "common.h"
27 
28 /*
29  * r8a7740 chip has lasting errata on MERAM buffer.
30  * this is work-around for it.
31  * see
32  *	"Media RAM (MERAM)" on r8a7740 documentation
33  */
34 #define MEBUFCNTR	0xFE950098
35 static void __init r8a7740_meram_workaround(void)
36 {
37 	void __iomem *reg;
38 
39 	reg = ioremap_nocache(MEBUFCNTR, 4);
40 	if (reg) {
41 		iowrite32(0x01600164, reg);
42 		iounmap(reg);
43 	}
44 }
45 
46 static void __init r8a7740_init_irq_of(void)
47 {
48 	void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
49 	void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
50 	void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
51 
52 	irqchip_init();
53 
54 	/* route signals to GIC */
55 	iowrite32(0x0, pfc_inta_ctrl);
56 
57 	/*
58 	 * To mask the shared interrupt to SPI 149 we must ensure to set
59 	 * PRIO *and* MASK. Else we run into IRQ floods when registering
60 	 * the intc_irqpin devices
61 	 */
62 	iowrite32(0x0, intc_prio_base + 0x0);
63 	iowrite32(0x0, intc_prio_base + 0x4);
64 	iowrite32(0x0, intc_prio_base + 0x8);
65 	iowrite32(0x0, intc_prio_base + 0xc);
66 	iowrite8(0xff, intc_msk_base + 0x0);
67 	iowrite8(0xff, intc_msk_base + 0x4);
68 	iowrite8(0xff, intc_msk_base + 0x8);
69 	iowrite8(0xff, intc_msk_base + 0xc);
70 
71 	iounmap(intc_prio_base);
72 	iounmap(intc_msk_base);
73 	iounmap(pfc_inta_ctrl);
74 }
75 
76 static void __init r8a7740_generic_init(void)
77 {
78 	r8a7740_meram_workaround();
79 }
80 
81 static const char *const r8a7740_boards_compat_dt[] __initconst = {
82 	"renesas,r8a7740",
83 	NULL,
84 };
85 
86 DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
87 	.l2c_aux_val	= 0,
88 	.l2c_aux_mask	= ~0,
89 	.init_early	= shmobile_init_delay,
90 	.init_irq	= r8a7740_init_irq_of,
91 	.init_machine	= r8a7740_generic_init,
92 	.init_late	= shmobile_init_late,
93 	.dt_compat	= r8a7740_boards_compat_dt,
94 MACHINE_END
95