1 /* 2 * R8A7740 processor support 3 * 4 * Copyright (C) 2011 Renesas Solutions Corp. 5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; version 2 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19 */ 20 #include <linux/delay.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/kernel.h> 23 #include <linux/init.h> 24 #include <linux/io.h> 25 #include <linux/irqchip.h> 26 #include <linux/irqchip/arm-gic.h> 27 #include <linux/platform_data/irq-renesas-intc-irqpin.h> 28 #include <linux/platform_device.h> 29 #include <linux/of_platform.h> 30 #include <linux/serial_sci.h> 31 #include <linux/sh_dma.h> 32 #include <linux/sh_timer.h> 33 #include <linux/platform_data/sh_ipmmu.h> 34 35 #include <asm/mach-types.h> 36 #include <asm/mach/map.h> 37 #include <asm/mach/arch.h> 38 #include <asm/mach/time.h> 39 40 #include "common.h" 41 #include "dma-register.h" 42 #include "irqs.h" 43 #include "pm-rmobile.h" 44 #include "r8a7740.h" 45 46 static struct map_desc r8a7740_io_desc[] __initdata = { 47 /* 48 * for CPGA/INTC/PFC 49 * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff 50 */ 51 { 52 .virtual = 0xe6000000, 53 .pfn = __phys_to_pfn(0xe6000000), 54 .length = 160 << 20, 55 .type = MT_DEVICE_NONSHARED 56 }, 57 #ifdef CONFIG_CACHE_L2X0 58 /* 59 * for l2x0_init() 60 * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000 61 */ 62 { 63 .virtual = 0xf0002000, 64 .pfn = __phys_to_pfn(0xf0100000), 65 .length = PAGE_SIZE, 66 .type = MT_DEVICE_NONSHARED 67 }, 68 #endif 69 }; 70 71 void __init r8a7740_map_io(void) 72 { 73 iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc)); 74 } 75 76 /* PFC */ 77 static const struct resource pfc_resources[] = { 78 DEFINE_RES_MEM(0xe6050000, 0x8000), 79 DEFINE_RES_MEM(0xe605800c, 0x0020), 80 }; 81 82 void __init r8a7740_pinmux_init(void) 83 { 84 platform_device_register_simple("pfc-r8a7740", -1, pfc_resources, 85 ARRAY_SIZE(pfc_resources)); 86 } 87 88 static struct renesas_intc_irqpin_config irqpin0_platform_data = { 89 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */ 90 }; 91 92 static struct resource irqpin0_resources[] = { 93 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */ 94 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */ 95 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */ 96 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */ 97 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */ 98 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */ 99 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */ 100 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */ 101 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */ 102 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */ 103 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */ 104 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */ 105 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */ 106 }; 107 108 static struct platform_device irqpin0_device = { 109 .name = "renesas_intc_irqpin", 110 .id = 0, 111 .resource = irqpin0_resources, 112 .num_resources = ARRAY_SIZE(irqpin0_resources), 113 .dev = { 114 .platform_data = &irqpin0_platform_data, 115 }, 116 }; 117 118 static struct renesas_intc_irqpin_config irqpin1_platform_data = { 119 .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */ 120 }; 121 122 static struct resource irqpin1_resources[] = { 123 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */ 124 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */ 125 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */ 126 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */ 127 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */ 128 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ8 */ 129 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ9 */ 130 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ10 */ 131 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ11 */ 132 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ12 */ 133 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ13 */ 134 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ14 */ 135 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ15 */ 136 }; 137 138 static struct platform_device irqpin1_device = { 139 .name = "renesas_intc_irqpin", 140 .id = 1, 141 .resource = irqpin1_resources, 142 .num_resources = ARRAY_SIZE(irqpin1_resources), 143 .dev = { 144 .platform_data = &irqpin1_platform_data, 145 }, 146 }; 147 148 static struct renesas_intc_irqpin_config irqpin2_platform_data = { 149 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */ 150 }; 151 152 static struct resource irqpin2_resources[] = { 153 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */ 154 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI30A */ 155 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ30A */ 156 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK30A */ 157 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR30A */ 158 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ16 */ 159 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ17 */ 160 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ18 */ 161 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ19 */ 162 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ20 */ 163 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ21 */ 164 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ22 */ 165 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ23 */ 166 }; 167 168 static struct platform_device irqpin2_device = { 169 .name = "renesas_intc_irqpin", 170 .id = 2, 171 .resource = irqpin2_resources, 172 .num_resources = ARRAY_SIZE(irqpin2_resources), 173 .dev = { 174 .platform_data = &irqpin2_platform_data, 175 }, 176 }; 177 178 static struct renesas_intc_irqpin_config irqpin3_platform_data = { 179 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */ 180 }; 181 182 static struct resource irqpin3_resources[] = { 183 DEFINE_RES_MEM(0xe690000c, 4), /* ICR3A */ 184 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */ 185 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */ 186 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */ 187 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */ 188 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ24 */ 189 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ25 */ 190 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ26 */ 191 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ27 */ 192 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ28 */ 193 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ29 */ 194 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ30 */ 195 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ31 */ 196 }; 197 198 static struct platform_device irqpin3_device = { 199 .name = "renesas_intc_irqpin", 200 .id = 3, 201 .resource = irqpin3_resources, 202 .num_resources = ARRAY_SIZE(irqpin3_resources), 203 .dev = { 204 .platform_data = &irqpin3_platform_data, 205 }, 206 }; 207 208 /* SCIF */ 209 #define R8A7740_SCIF(scif_type, index, baseaddr, irq) \ 210 static struct plat_sci_port scif##index##_platform_data = { \ 211 .type = scif_type, \ 212 .flags = UPF_BOOT_AUTOCONF, \ 213 .scscr = SCSCR_RE | SCSCR_TE, \ 214 }; \ 215 \ 216 static struct resource scif##index##_resources[] = { \ 217 DEFINE_RES_MEM(baseaddr, 0x100), \ 218 DEFINE_RES_IRQ(irq), \ 219 }; \ 220 \ 221 static struct platform_device scif##index##_device = { \ 222 .name = "sh-sci", \ 223 .id = index, \ 224 .resource = scif##index##_resources, \ 225 .num_resources = ARRAY_SIZE(scif##index##_resources), \ 226 .dev = { \ 227 .platform_data = &scif##index##_platform_data, \ 228 }, \ 229 } 230 231 R8A7740_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(100)); 232 R8A7740_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(101)); 233 R8A7740_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(102)); 234 R8A7740_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(103)); 235 R8A7740_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(104)); 236 R8A7740_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(105)); 237 R8A7740_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(106)); 238 R8A7740_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(107)); 239 R8A7740_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(108)); 240 241 /* CMT */ 242 static struct sh_timer_config cmt1_platform_data = { 243 .channels_mask = 0x3f, 244 }; 245 246 static struct resource cmt1_resources[] = { 247 DEFINE_RES_MEM(0xe6138000, 0x170), 248 DEFINE_RES_IRQ(gic_spi(58)), 249 }; 250 251 static struct platform_device cmt1_device = { 252 .name = "sh-cmt-48", 253 .id = 1, 254 .dev = { 255 .platform_data = &cmt1_platform_data, 256 }, 257 .resource = cmt1_resources, 258 .num_resources = ARRAY_SIZE(cmt1_resources), 259 }; 260 261 /* TMU */ 262 static struct sh_timer_config tmu0_platform_data = { 263 .channels_mask = 7, 264 }; 265 266 static struct resource tmu0_resources[] = { 267 DEFINE_RES_MEM(0xfff80000, 0x2c), 268 DEFINE_RES_IRQ(gic_spi(198)), 269 DEFINE_RES_IRQ(gic_spi(199)), 270 DEFINE_RES_IRQ(gic_spi(200)), 271 }; 272 273 static struct platform_device tmu0_device = { 274 .name = "sh-tmu", 275 .id = 0, 276 .dev = { 277 .platform_data = &tmu0_platform_data, 278 }, 279 .resource = tmu0_resources, 280 .num_resources = ARRAY_SIZE(tmu0_resources), 281 }; 282 283 /* IPMMUI (an IPMMU module for ICB/LMB) */ 284 static struct resource ipmmu_resources[] = { 285 [0] = { 286 .name = "IPMMUI", 287 .start = 0xfe951000, 288 .end = 0xfe9510ff, 289 .flags = IORESOURCE_MEM, 290 }, 291 }; 292 293 static const char * const ipmmu_dev_names[] = { 294 "sh_mobile_lcdc_fb.0", 295 "sh_mobile_lcdc_fb.1", 296 "sh_mobile_ceu.0", 297 }; 298 299 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = { 300 .dev_names = ipmmu_dev_names, 301 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names), 302 }; 303 304 static struct platform_device ipmmu_device = { 305 .name = "ipmmu", 306 .id = -1, 307 .dev = { 308 .platform_data = &ipmmu_platform_data, 309 }, 310 .resource = ipmmu_resources, 311 .num_resources = ARRAY_SIZE(ipmmu_resources), 312 }; 313 314 static struct platform_device *r8a7740_devices_dt[] __initdata = { 315 &cmt1_device, 316 }; 317 318 static struct platform_device *r8a7740_early_devices[] __initdata = { 319 &scif0_device, 320 &scif1_device, 321 &scif2_device, 322 &scif3_device, 323 &scif4_device, 324 &scif5_device, 325 &scif6_device, 326 &scif7_device, 327 &scif8_device, 328 &irqpin0_device, 329 &irqpin1_device, 330 &irqpin2_device, 331 &irqpin3_device, 332 &tmu0_device, 333 &ipmmu_device, 334 }; 335 336 /* DMA */ 337 static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = { 338 { 339 .slave_id = SHDMA_SLAVE_SDHI0_TX, 340 .addr = 0xe6850030, 341 .chcr = CHCR_TX(XMIT_SZ_16BIT), 342 .mid_rid = 0xc1, 343 }, { 344 .slave_id = SHDMA_SLAVE_SDHI0_RX, 345 .addr = 0xe6850030, 346 .chcr = CHCR_RX(XMIT_SZ_16BIT), 347 .mid_rid = 0xc2, 348 }, { 349 .slave_id = SHDMA_SLAVE_SDHI1_TX, 350 .addr = 0xe6860030, 351 .chcr = CHCR_TX(XMIT_SZ_16BIT), 352 .mid_rid = 0xc9, 353 }, { 354 .slave_id = SHDMA_SLAVE_SDHI1_RX, 355 .addr = 0xe6860030, 356 .chcr = CHCR_RX(XMIT_SZ_16BIT), 357 .mid_rid = 0xca, 358 }, { 359 .slave_id = SHDMA_SLAVE_SDHI2_TX, 360 .addr = 0xe6870030, 361 .chcr = CHCR_TX(XMIT_SZ_16BIT), 362 .mid_rid = 0xcd, 363 }, { 364 .slave_id = SHDMA_SLAVE_SDHI2_RX, 365 .addr = 0xe6870030, 366 .chcr = CHCR_RX(XMIT_SZ_16BIT), 367 .mid_rid = 0xce, 368 }, { 369 .slave_id = SHDMA_SLAVE_FSIA_TX, 370 .addr = 0xfe1f0024, 371 .chcr = CHCR_TX(XMIT_SZ_32BIT), 372 .mid_rid = 0xb1, 373 }, { 374 .slave_id = SHDMA_SLAVE_FSIA_RX, 375 .addr = 0xfe1f0020, 376 .chcr = CHCR_RX(XMIT_SZ_32BIT), 377 .mid_rid = 0xb2, 378 }, { 379 .slave_id = SHDMA_SLAVE_FSIB_TX, 380 .addr = 0xfe1f0064, 381 .chcr = CHCR_TX(XMIT_SZ_32BIT), 382 .mid_rid = 0xb5, 383 }, { 384 .slave_id = SHDMA_SLAVE_MMCIF_TX, 385 .addr = 0xe6bd0034, 386 .chcr = CHCR_TX(XMIT_SZ_32BIT), 387 .mid_rid = 0xd1, 388 }, { 389 .slave_id = SHDMA_SLAVE_MMCIF_RX, 390 .addr = 0xe6bd0034, 391 .chcr = CHCR_RX(XMIT_SZ_32BIT), 392 .mid_rid = 0xd2, 393 }, 394 }; 395 396 #define DMA_CHANNEL(a, b, c) \ 397 { \ 398 .offset = a, \ 399 .dmars = b, \ 400 .dmars_bit = c, \ 401 .chclr_offset = (0x220 - 0x20) + a \ 402 } 403 404 static const struct sh_dmae_channel r8a7740_dmae_channels[] = { 405 DMA_CHANNEL(0x00, 0, 0), 406 DMA_CHANNEL(0x10, 0, 8), 407 DMA_CHANNEL(0x20, 4, 0), 408 DMA_CHANNEL(0x30, 4, 8), 409 DMA_CHANNEL(0x50, 8, 0), 410 DMA_CHANNEL(0x60, 8, 8), 411 }; 412 413 static struct sh_dmae_pdata dma_platform_data = { 414 .slave = r8a7740_dmae_slaves, 415 .slave_num = ARRAY_SIZE(r8a7740_dmae_slaves), 416 .channel = r8a7740_dmae_channels, 417 .channel_num = ARRAY_SIZE(r8a7740_dmae_channels), 418 .ts_low_shift = TS_LOW_SHIFT, 419 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, 420 .ts_high_shift = TS_HI_SHIFT, 421 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, 422 .ts_shift = dma_ts_shift, 423 .ts_shift_num = ARRAY_SIZE(dma_ts_shift), 424 .dmaor_init = DMAOR_DME, 425 .chclr_present = 1, 426 }; 427 428 /* Resource order important! */ 429 static struct resource r8a7740_dmae0_resources[] = { 430 { 431 /* Channel registers and DMAOR */ 432 .start = 0xfe008020, 433 .end = 0xfe00828f, 434 .flags = IORESOURCE_MEM, 435 }, 436 { 437 /* DMARSx */ 438 .start = 0xfe009000, 439 .end = 0xfe00900b, 440 .flags = IORESOURCE_MEM, 441 }, 442 { 443 .name = "error_irq", 444 .start = gic_spi(34), 445 .end = gic_spi(34), 446 .flags = IORESOURCE_IRQ, 447 }, 448 { 449 /* IRQ for channels 0-5 */ 450 .start = gic_spi(28), 451 .end = gic_spi(33), 452 .flags = IORESOURCE_IRQ, 453 }, 454 }; 455 456 /* Resource order important! */ 457 static struct resource r8a7740_dmae1_resources[] = { 458 { 459 /* Channel registers and DMAOR */ 460 .start = 0xfe018020, 461 .end = 0xfe01828f, 462 .flags = IORESOURCE_MEM, 463 }, 464 { 465 /* DMARSx */ 466 .start = 0xfe019000, 467 .end = 0xfe01900b, 468 .flags = IORESOURCE_MEM, 469 }, 470 { 471 .name = "error_irq", 472 .start = gic_spi(41), 473 .end = gic_spi(41), 474 .flags = IORESOURCE_IRQ, 475 }, 476 { 477 /* IRQ for channels 0-5 */ 478 .start = gic_spi(35), 479 .end = gic_spi(40), 480 .flags = IORESOURCE_IRQ, 481 }, 482 }; 483 484 /* Resource order important! */ 485 static struct resource r8a7740_dmae2_resources[] = { 486 { 487 /* Channel registers and DMAOR */ 488 .start = 0xfe028020, 489 .end = 0xfe02828f, 490 .flags = IORESOURCE_MEM, 491 }, 492 { 493 /* DMARSx */ 494 .start = 0xfe029000, 495 .end = 0xfe02900b, 496 .flags = IORESOURCE_MEM, 497 }, 498 { 499 .name = "error_irq", 500 .start = gic_spi(48), 501 .end = gic_spi(48), 502 .flags = IORESOURCE_IRQ, 503 }, 504 { 505 /* IRQ for channels 0-5 */ 506 .start = gic_spi(42), 507 .end = gic_spi(47), 508 .flags = IORESOURCE_IRQ, 509 }, 510 }; 511 512 static struct platform_device dma0_device = { 513 .name = "sh-dma-engine", 514 .id = 0, 515 .resource = r8a7740_dmae0_resources, 516 .num_resources = ARRAY_SIZE(r8a7740_dmae0_resources), 517 .dev = { 518 .platform_data = &dma_platform_data, 519 }, 520 }; 521 522 static struct platform_device dma1_device = { 523 .name = "sh-dma-engine", 524 .id = 1, 525 .resource = r8a7740_dmae1_resources, 526 .num_resources = ARRAY_SIZE(r8a7740_dmae1_resources), 527 .dev = { 528 .platform_data = &dma_platform_data, 529 }, 530 }; 531 532 static struct platform_device dma2_device = { 533 .name = "sh-dma-engine", 534 .id = 2, 535 .resource = r8a7740_dmae2_resources, 536 .num_resources = ARRAY_SIZE(r8a7740_dmae2_resources), 537 .dev = { 538 .platform_data = &dma_platform_data, 539 }, 540 }; 541 542 /* USB-DMAC */ 543 static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = { 544 { 545 .offset = 0, 546 }, { 547 .offset = 0x20, 548 }, 549 }; 550 551 static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = { 552 { 553 .slave_id = SHDMA_SLAVE_USBHS_TX, 554 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE), 555 }, { 556 .slave_id = SHDMA_SLAVE_USBHS_RX, 557 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE), 558 }, 559 }; 560 561 static struct sh_dmae_pdata usb_dma_platform_data = { 562 .slave = r8a7740_usb_dma_slaves, 563 .slave_num = ARRAY_SIZE(r8a7740_usb_dma_slaves), 564 .channel = r8a7740_usb_dma_channels, 565 .channel_num = ARRAY_SIZE(r8a7740_usb_dma_channels), 566 .ts_low_shift = USBTS_LOW_SHIFT, 567 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT, 568 .ts_high_shift = USBTS_HI_SHIFT, 569 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT, 570 .ts_shift = dma_usbts_shift, 571 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift), 572 .dmaor_init = DMAOR_DME, 573 .chcr_offset = 0x14, 574 .chcr_ie_bit = 1 << 5, 575 .dmaor_is_32bit = 1, 576 .needs_tend_set = 1, 577 .no_dmars = 1, 578 .slave_only = 1, 579 }; 580 581 static struct resource r8a7740_usb_dma_resources[] = { 582 { 583 /* Channel registers and DMAOR */ 584 .start = 0xe68a0020, 585 .end = 0xe68a0064 - 1, 586 .flags = IORESOURCE_MEM, 587 }, 588 { 589 /* VCR/SWR/DMICR */ 590 .start = 0xe68a0000, 591 .end = 0xe68a0014 - 1, 592 .flags = IORESOURCE_MEM, 593 }, 594 { 595 /* IRQ for channels */ 596 .start = gic_spi(49), 597 .end = gic_spi(49), 598 .flags = IORESOURCE_IRQ, 599 }, 600 }; 601 602 static struct platform_device usb_dma_device = { 603 .name = "sh-dma-engine", 604 .id = 3, 605 .resource = r8a7740_usb_dma_resources, 606 .num_resources = ARRAY_SIZE(r8a7740_usb_dma_resources), 607 .dev = { 608 .platform_data = &usb_dma_platform_data, 609 }, 610 }; 611 612 /* I2C */ 613 static struct resource i2c0_resources[] = { 614 [0] = { 615 .name = "IIC0", 616 .start = 0xfff20000, 617 .end = 0xfff20425 - 1, 618 .flags = IORESOURCE_MEM, 619 }, 620 [1] = { 621 .start = gic_spi(201), 622 .end = gic_spi(204), 623 .flags = IORESOURCE_IRQ, 624 }, 625 }; 626 627 static struct resource i2c1_resources[] = { 628 [0] = { 629 .name = "IIC1", 630 .start = 0xe6c20000, 631 .end = 0xe6c20425 - 1, 632 .flags = IORESOURCE_MEM, 633 }, 634 [1] = { 635 .start = gic_spi(70), /* IIC1_ALI1 */ 636 .end = gic_spi(73), /* IIC1_DTEI1 */ 637 .flags = IORESOURCE_IRQ, 638 }, 639 }; 640 641 static struct platform_device i2c0_device = { 642 .name = "i2c-sh_mobile", 643 .id = 0, 644 .resource = i2c0_resources, 645 .num_resources = ARRAY_SIZE(i2c0_resources), 646 }; 647 648 static struct platform_device i2c1_device = { 649 .name = "i2c-sh_mobile", 650 .id = 1, 651 .resource = i2c1_resources, 652 .num_resources = ARRAY_SIZE(i2c1_resources), 653 }; 654 655 static struct resource pmu_resources[] = { 656 [0] = { 657 .start = gic_spi(83), 658 .end = gic_spi(83), 659 .flags = IORESOURCE_IRQ, 660 }, 661 }; 662 663 static struct platform_device pmu_device = { 664 .name = "arm-pmu", 665 .id = -1, 666 .num_resources = ARRAY_SIZE(pmu_resources), 667 .resource = pmu_resources, 668 }; 669 670 static struct platform_device *r8a7740_late_devices[] __initdata = { 671 &i2c0_device, 672 &i2c1_device, 673 &dma0_device, 674 &dma1_device, 675 &dma2_device, 676 &usb_dma_device, 677 &pmu_device, 678 }; 679 680 /* 681 * r8a7740 chip has lasting errata on MERAM buffer. 682 * this is work-around for it. 683 * see 684 * "Media RAM (MERAM)" on r8a7740 documentation 685 */ 686 #define MEBUFCNTR 0xFE950098 687 void __init r8a7740_meram_workaround(void) 688 { 689 void __iomem *reg; 690 691 reg = ioremap_nocache(MEBUFCNTR, 4); 692 if (reg) { 693 iowrite32(0x01600164, reg); 694 iounmap(reg); 695 } 696 } 697 698 #define ICCR 0x0004 699 #define ICSTART 0x0070 700 701 #define i2c_read(reg, offset) ioread8(reg + offset) 702 #define i2c_write(reg, offset, data) iowrite8(data, reg + offset) 703 704 /* 705 * r8a7740 chip has lasting errata on I2C I/O pad reset. 706 * this is work-around for it. 707 */ 708 static void r8a7740_i2c_workaround(struct platform_device *pdev) 709 { 710 struct resource *res; 711 void __iomem *reg; 712 713 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 714 if (unlikely(!res)) { 715 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n"); 716 return; 717 } 718 719 reg = ioremap(res->start, resource_size(res)); 720 if (unlikely(!reg)) { 721 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n"); 722 return; 723 } 724 725 i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80); 726 i2c_read(reg, ICCR); /* dummy read */ 727 728 i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10); 729 i2c_read(reg, ICSTART); /* dummy read */ 730 731 udelay(10); 732 733 i2c_write(reg, ICCR, 0x01); 734 i2c_write(reg, ICSTART, 0x00); 735 736 udelay(10); 737 738 i2c_write(reg, ICCR, 0x10); 739 udelay(10); 740 i2c_write(reg, ICCR, 0x00); 741 udelay(10); 742 i2c_write(reg, ICCR, 0x10); 743 udelay(10); 744 745 iounmap(reg); 746 } 747 748 void __init r8a7740_add_standard_devices(void) 749 { 750 /* I2C work-around */ 751 r8a7740_i2c_workaround(&i2c0_device); 752 r8a7740_i2c_workaround(&i2c1_device); 753 754 r8a7740_init_pm_domains(); 755 756 /* add devices */ 757 platform_add_devices(r8a7740_early_devices, 758 ARRAY_SIZE(r8a7740_early_devices)); 759 platform_add_devices(r8a7740_devices_dt, 760 ARRAY_SIZE(r8a7740_devices_dt)); 761 platform_add_devices(r8a7740_late_devices, 762 ARRAY_SIZE(r8a7740_late_devices)); 763 764 /* add devices to PM domain */ 765 766 rmobile_add_device_to_domain("A3SP", &scif0_device); 767 rmobile_add_device_to_domain("A3SP", &scif1_device); 768 rmobile_add_device_to_domain("A3SP", &scif2_device); 769 rmobile_add_device_to_domain("A3SP", &scif3_device); 770 rmobile_add_device_to_domain("A3SP", &scif4_device); 771 rmobile_add_device_to_domain("A3SP", &scif5_device); 772 rmobile_add_device_to_domain("A3SP", &scif6_device); 773 rmobile_add_device_to_domain("A3SP", &scif7_device); 774 rmobile_add_device_to_domain("A3SP", &scif8_device); 775 rmobile_add_device_to_domain("A3SP", &i2c1_device); 776 } 777 778 void __init r8a7740_add_early_devices(void) 779 { 780 early_platform_add_devices(r8a7740_early_devices, 781 ARRAY_SIZE(r8a7740_early_devices)); 782 early_platform_add_devices(r8a7740_devices_dt, 783 ARRAY_SIZE(r8a7740_devices_dt)); 784 785 /* setup early console here as well */ 786 shmobile_setup_console(); 787 } 788 789 #ifdef CONFIG_USE_OF 790 791 void __init r8a7740_add_standard_devices_dt(void) 792 { 793 platform_add_devices(r8a7740_devices_dt, 794 ARRAY_SIZE(r8a7740_devices_dt)); 795 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 796 } 797 798 void __init r8a7740_init_irq_of(void) 799 { 800 void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10); 801 void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10); 802 void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4); 803 804 irqchip_init(); 805 806 /* route signals to GIC */ 807 iowrite32(0x0, pfc_inta_ctrl); 808 809 /* 810 * To mask the shared interrupt to SPI 149 we must ensure to set 811 * PRIO *and* MASK. Else we run into IRQ floods when registering 812 * the intc_irqpin devices 813 */ 814 iowrite32(0x0, intc_prio_base + 0x0); 815 iowrite32(0x0, intc_prio_base + 0x4); 816 iowrite32(0x0, intc_prio_base + 0x8); 817 iowrite32(0x0, intc_prio_base + 0xc); 818 iowrite8(0xff, intc_msk_base + 0x0); 819 iowrite8(0xff, intc_msk_base + 0x4); 820 iowrite8(0xff, intc_msk_base + 0x8); 821 iowrite8(0xff, intc_msk_base + 0xc); 822 823 iounmap(intc_prio_base); 824 iounmap(intc_msk_base); 825 iounmap(pfc_inta_ctrl); 826 } 827 828 static void __init r8a7740_generic_init(void) 829 { 830 r8a7740_clock_init(0); 831 r8a7740_add_standard_devices_dt(); 832 } 833 834 static const char *r8a7740_boards_compat_dt[] __initdata = { 835 "renesas,r8a7740", 836 NULL, 837 }; 838 839 DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)") 840 .map_io = r8a7740_map_io, 841 .init_early = shmobile_init_delay, 842 .init_irq = r8a7740_init_irq_of, 843 .init_machine = r8a7740_generic_init, 844 .init_late = shmobile_init_late, 845 .dt_compat = r8a7740_boards_compat_dt, 846 MACHINE_END 847 848 #endif /* CONFIG_USE_OF */ 849