1 /* 2 * r8a73a4 processor support 3 * 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Magnus Damm 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; version 2 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19 */ 20 #include <linux/irq.h> 21 #include <linux/kernel.h> 22 #include <linux/of_platform.h> 23 #include <linux/platform_data/irq-renesas-irqc.h> 24 #include <linux/serial_sci.h> 25 #include <linux/sh_dma.h> 26 #include <linux/sh_timer.h> 27 #include <mach/r8a73a4.h> 28 #include <asm/mach/arch.h> 29 #include "common.h" 30 #include "dma-register.h" 31 #include "irqs.h" 32 33 static const struct resource pfc_resources[] = { 34 DEFINE_RES_MEM(0xe6050000, 0x9000), 35 }; 36 37 void __init r8a73a4_pinmux_init(void) 38 { 39 platform_device_register_simple("pfc-r8a73a4", -1, pfc_resources, 40 ARRAY_SIZE(pfc_resources)); 41 } 42 43 #define R8A73A4_SCIF(scif_type, _scscr, index, baseaddr, irq) \ 44 static struct plat_sci_port scif##index##_platform_data = { \ 45 .type = scif_type, \ 46 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 47 .scscr = _scscr, \ 48 }; \ 49 \ 50 static struct resource scif##index##_resources[] = { \ 51 DEFINE_RES_MEM(baseaddr, 0x100), \ 52 DEFINE_RES_IRQ(irq), \ 53 } 54 55 #define R8A73A4_SCIFA(index, baseaddr, irq) \ 56 R8A73A4_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \ 57 index, baseaddr, irq) 58 59 #define R8A73A4_SCIFB(index, baseaddr, irq) \ 60 R8A73A4_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \ 61 index, baseaddr, irq) 62 63 R8A73A4_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */ 64 R8A73A4_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */ 65 R8A73A4_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */ 66 R8A73A4_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */ 67 R8A73A4_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */ 68 R8A73A4_SCIFB(5, 0xe6cf0000, gic_spi(151)); /* SCIFB3 */ 69 70 #define r8a73a4_register_scif(index) \ 71 platform_device_register_resndata(&platform_bus, "sh-sci", index, \ 72 scif##index##_resources, \ 73 ARRAY_SIZE(scif##index##_resources), \ 74 &scif##index##_platform_data, \ 75 sizeof(scif##index##_platform_data)) 76 77 static const struct renesas_irqc_config irqc0_data = { 78 .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */ 79 }; 80 81 static const struct resource irqc0_resources[] = { 82 DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */ 83 DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */ 84 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */ 85 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */ 86 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */ 87 DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */ 88 DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */ 89 DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */ 90 DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */ 91 DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */ 92 DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */ 93 DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */ 94 DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */ 95 DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */ 96 DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */ 97 DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */ 98 DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */ 99 DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */ 100 DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */ 101 DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */ 102 DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */ 103 DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */ 104 DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */ 105 DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */ 106 DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */ 107 DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */ 108 DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */ 109 DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */ 110 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */ 111 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */ 112 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */ 113 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */ 114 DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */ 115 }; 116 117 static const struct renesas_irqc_config irqc1_data = { 118 .irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */ 119 }; 120 121 static const struct resource irqc1_resources[] = { 122 DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */ 123 DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */ 124 DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */ 125 DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */ 126 DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */ 127 DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */ 128 DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */ 129 DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */ 130 DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */ 131 DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */ 132 DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */ 133 DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */ 134 DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */ 135 DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */ 136 DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */ 137 DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */ 138 DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */ 139 DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */ 140 DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */ 141 DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */ 142 DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */ 143 DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */ 144 DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */ 145 DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */ 146 DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */ 147 DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */ 148 DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */ 149 }; 150 151 #define r8a73a4_register_irqc(idx) \ 152 platform_device_register_resndata(&platform_bus, "renesas_irqc", \ 153 idx, irqc##idx##_resources, \ 154 ARRAY_SIZE(irqc##idx##_resources), \ 155 &irqc##idx##_data, \ 156 sizeof(struct renesas_irqc_config)) 157 158 /* Thermal0 -> Thermal2 */ 159 static const struct resource thermal0_resources[] = { 160 DEFINE_RES_MEM(0xe61f0000, 0x14), 161 DEFINE_RES_MEM(0xe61f0100, 0x38), 162 DEFINE_RES_MEM(0xe61f0200, 0x38), 163 DEFINE_RES_MEM(0xe61f0300, 0x38), 164 DEFINE_RES_IRQ(gic_spi(69)), 165 }; 166 167 #define r8a73a4_register_thermal() \ 168 platform_device_register_simple("rcar_thermal", -1, \ 169 thermal0_resources, \ 170 ARRAY_SIZE(thermal0_resources)) 171 172 static struct sh_timer_config cmt1_platform_data = { 173 .channels_mask = 0xff, 174 }; 175 176 static struct resource cmt1_resources[] = { 177 DEFINE_RES_MEM(0xe6130000, 0x1004), 178 DEFINE_RES_IRQ(gic_spi(120)), 179 }; 180 181 #define r8a7790_register_cmt(idx) \ 182 platform_device_register_resndata(&platform_bus, "sh-cmt-48-gen2", \ 183 idx, cmt##idx##_resources, \ 184 ARRAY_SIZE(cmt##idx##_resources), \ 185 &cmt##idx##_platform_data, \ 186 sizeof(struct sh_timer_config)) 187 188 void __init r8a73a4_add_dt_devices(void) 189 { 190 r8a73a4_register_scif(0); 191 r8a73a4_register_scif(1); 192 r8a73a4_register_scif(2); 193 r8a73a4_register_scif(3); 194 r8a73a4_register_scif(4); 195 r8a73a4_register_scif(5); 196 r8a7790_register_cmt(1); 197 } 198 199 /* DMA */ 200 static const struct sh_dmae_slave_config dma_slaves[] = { 201 { 202 .slave_id = SHDMA_SLAVE_MMCIF0_TX, 203 .addr = 0xee200034, 204 .chcr = CHCR_TX(XMIT_SZ_32BIT), 205 .mid_rid = 0xd1, 206 }, { 207 .slave_id = SHDMA_SLAVE_MMCIF0_RX, 208 .addr = 0xee200034, 209 .chcr = CHCR_RX(XMIT_SZ_32BIT), 210 .mid_rid = 0xd2, 211 }, { 212 .slave_id = SHDMA_SLAVE_MMCIF1_TX, 213 .addr = 0xee220034, 214 .chcr = CHCR_TX(XMIT_SZ_32BIT), 215 .mid_rid = 0xe1, 216 }, { 217 .slave_id = SHDMA_SLAVE_MMCIF1_RX, 218 .addr = 0xee220034, 219 .chcr = CHCR_RX(XMIT_SZ_32BIT), 220 .mid_rid = 0xe2, 221 }, 222 }; 223 224 #define DMAE_CHANNEL(a, b) \ 225 { \ 226 .offset = (a) - 0x20, \ 227 .dmars = (a) - 0x20 + 0x40, \ 228 .chclr_bit = (b), \ 229 .chclr_offset = 0x80 - 0x20, \ 230 } 231 232 static const struct sh_dmae_channel dma_channels[] = { 233 DMAE_CHANNEL(0x8000, 0), 234 DMAE_CHANNEL(0x8080, 1), 235 DMAE_CHANNEL(0x8100, 2), 236 DMAE_CHANNEL(0x8180, 3), 237 DMAE_CHANNEL(0x8200, 4), 238 DMAE_CHANNEL(0x8280, 5), 239 DMAE_CHANNEL(0x8300, 6), 240 DMAE_CHANNEL(0x8380, 7), 241 DMAE_CHANNEL(0x8400, 8), 242 DMAE_CHANNEL(0x8480, 9), 243 DMAE_CHANNEL(0x8500, 10), 244 DMAE_CHANNEL(0x8580, 11), 245 DMAE_CHANNEL(0x8600, 12), 246 DMAE_CHANNEL(0x8680, 13), 247 DMAE_CHANNEL(0x8700, 14), 248 DMAE_CHANNEL(0x8780, 15), 249 DMAE_CHANNEL(0x8800, 16), 250 DMAE_CHANNEL(0x8880, 17), 251 DMAE_CHANNEL(0x8900, 18), 252 DMAE_CHANNEL(0x8980, 19), 253 }; 254 255 static const struct sh_dmae_pdata dma_pdata = { 256 .slave = dma_slaves, 257 .slave_num = ARRAY_SIZE(dma_slaves), 258 .channel = dma_channels, 259 .channel_num = ARRAY_SIZE(dma_channels), 260 .ts_low_shift = TS_LOW_SHIFT, 261 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, 262 .ts_high_shift = TS_HI_SHIFT, 263 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, 264 .ts_shift = dma_ts_shift, 265 .ts_shift_num = ARRAY_SIZE(dma_ts_shift), 266 .dmaor_init = DMAOR_DME, 267 .chclr_present = 1, 268 .chclr_bitwise = 1, 269 }; 270 271 static struct resource dma_resources[] = { 272 DEFINE_RES_MEM(0xe6700020, 0x89e0), 273 DEFINE_RES_IRQ(gic_spi(220)), 274 { 275 /* IRQ for channels 0-19 */ 276 .start = gic_spi(200), 277 .end = gic_spi(219), 278 .flags = IORESOURCE_IRQ, 279 }, 280 }; 281 282 #define r8a73a4_register_dmac() \ 283 platform_device_register_resndata(&platform_bus, "sh-dma-engine", 0, \ 284 dma_resources, ARRAY_SIZE(dma_resources), \ 285 &dma_pdata, sizeof(dma_pdata)) 286 287 void __init r8a73a4_add_standard_devices(void) 288 { 289 r8a73a4_add_dt_devices(); 290 r8a73a4_register_irqc(0); 291 r8a73a4_register_irqc(1); 292 r8a73a4_register_thermal(); 293 r8a73a4_register_dmac(); 294 } 295 296 void __init r8a73a4_init_early(void) 297 { 298 #ifndef CONFIG_ARM_ARCH_TIMER 299 shmobile_setup_delay(1500, 2, 4); /* Cortex-A15 @ 1500MHz */ 300 #endif 301 } 302 303 #ifdef CONFIG_USE_OF 304 305 static const char *r8a73a4_boards_compat_dt[] __initdata = { 306 "renesas,r8a73a4", 307 NULL, 308 }; 309 310 DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)") 311 .init_early = r8a73a4_init_early, 312 .dt_compat = r8a73a4_boards_compat_dt, 313 MACHINE_END 314 #endif /* CONFIG_USE_OF */ 315