1 /* 2 * r7s72100 processor support 3 * 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Magnus Damm 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; version 2 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19 */ 20 21 #include <linux/irq.h> 22 #include <linux/kernel.h> 23 #include <linux/of_platform.h> 24 #include <linux/serial_sci.h> 25 #include <linux/sh_timer.h> 26 #include <mach/common.h> 27 #include <mach/irqs.h> 28 #include <mach/r7s72100.h> 29 #include <asm/mach/arch.h> 30 31 #define SCIF_DATA(index, baseaddr, irq) \ 32 [index] = { \ 33 .type = PORT_SCIF, \ 34 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, \ 35 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 36 .scbrr_algo_id = SCBRR_ALGO_2, \ 37 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | \ 38 SCSCR_REIE, \ 39 .mapbase = baseaddr, \ 40 .irqs = { irq + 1, irq + 2, irq + 3, irq }, \ 41 } 42 43 enum { SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7 }; 44 45 static const struct plat_sci_port scif[] __initconst = { 46 SCIF_DATA(SCIF0, 0xe8007000, gic_iid(221)), /* SCIF0 */ 47 SCIF_DATA(SCIF1, 0xe8007800, gic_iid(225)), /* SCIF1 */ 48 SCIF_DATA(SCIF2, 0xe8008000, gic_iid(229)), /* SCIF2 */ 49 SCIF_DATA(SCIF3, 0xe8008800, gic_iid(233)), /* SCIF3 */ 50 SCIF_DATA(SCIF4, 0xe8009000, gic_iid(237)), /* SCIF4 */ 51 SCIF_DATA(SCIF5, 0xe8009800, gic_iid(241)), /* SCIF5 */ 52 SCIF_DATA(SCIF6, 0xe800a000, gic_iid(245)), /* SCIF6 */ 53 SCIF_DATA(SCIF7, 0xe800a800, gic_iid(249)), /* SCIF7 */ 54 }; 55 56 static inline void r7s72100_register_scif(int idx) 57 { 58 platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], 59 sizeof(struct plat_sci_port)); 60 } 61 62 63 static struct sh_timer_config mtu2_0_platform_data __initdata = { 64 .name = "MTU2_0", 65 .timer_bit = 0, 66 .channel_offset = -0x80, 67 .clockevent_rating = 200, 68 }; 69 70 static struct resource mtu2_0_resources[] __initdata = { 71 DEFINE_RES_MEM(0xfcff0300, 0x27), 72 DEFINE_RES_IRQ(gic_iid(139)), /* MTU2 TGI0A */ 73 }; 74 75 #define r7s72100_register_mtu2(idx) \ 76 platform_device_register_resndata(&platform_bus, "sh_mtu2", \ 77 idx, mtu2_##idx##_resources, \ 78 ARRAY_SIZE(mtu2_##idx##_resources), \ 79 &mtu2_##idx##_platform_data, \ 80 sizeof(struct sh_timer_config)) 81 82 void __init r7s72100_add_dt_devices(void) 83 { 84 r7s72100_register_scif(SCIF0); 85 r7s72100_register_scif(SCIF1); 86 r7s72100_register_scif(SCIF2); 87 r7s72100_register_scif(SCIF3); 88 r7s72100_register_scif(SCIF4); 89 r7s72100_register_scif(SCIF5); 90 r7s72100_register_scif(SCIF6); 91 r7s72100_register_scif(SCIF7); 92 r7s72100_register_mtu2(0); 93 } 94 95 void __init r7s72100_init_early(void) 96 { 97 shmobile_setup_delay(400, 1, 3); /* Cortex-A9 @ 400MHz */ 98 } 99 100 #ifdef CONFIG_USE_OF 101 static const char *r7s72100_boards_compat_dt[] __initdata = { 102 "renesas,r7s72100", 103 NULL, 104 }; 105 106 DT_MACHINE_START(R7S72100_DT, "Generic R7S72100 (Flattened Device Tree)") 107 .init_early = r7s72100_init_early, 108 .dt_compat = r7s72100_boards_compat_dt, 109 MACHINE_END 110 #endif /* CONFIG_USE_OF */ 111