1 /* 2 * R-Car Generation 2 Power management support 3 * 4 * Copyright (C) 2013 - 2015 Renesas Electronics Corporation 5 * Copyright (C) 2011 Renesas Solutions Corp. 6 * Copyright (C) 2011 Magnus Damm 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/of.h> 15 #include <linux/smp.h> 16 #include <linux/soc/renesas/rcar-sysc.h> 17 #include <asm/io.h> 18 #include "common.h" 19 #include "rcar-gen2.h" 20 21 /* RST */ 22 #define RST 0xe6160000 23 #define CA15BAR 0x0020 24 #define CA7BAR 0x0030 25 #define CA15RESCNT 0x0040 26 #define CA7RESCNT 0x0044 27 28 /* On-chip RAM */ 29 #define ICRAM1 0xe63c0000 /* Inter Connect RAM1 (4 KiB) */ 30 31 /* SYSC */ 32 #define SYSCIER 0x0c 33 #define SYSCIMR 0x10 34 35 #if defined(CONFIG_SMP) 36 37 static void __init rcar_gen2_sysc_init(u32 syscier) 38 { 39 void __iomem *base = rcar_sysc_init(0xe6180000); 40 41 /* enable all interrupt sources, but do not use interrupt handler */ 42 iowrite32(syscier, base + SYSCIER); 43 iowrite32(0, base + SYSCIMR); 44 } 45 46 #else /* CONFIG_SMP */ 47 48 static inline void rcar_gen2_sysc_init(u32 syscier) {} 49 50 #endif /* CONFIG_SMP */ 51 52 void __init rcar_gen2_pm_init(void) 53 { 54 void __iomem *p; 55 u32 bar; 56 static int once; 57 struct device_node *np, *cpus; 58 bool has_a7 = false; 59 bool has_a15 = false; 60 phys_addr_t boot_vector_addr = ICRAM1; 61 u32 syscier = 0; 62 63 if (once++) 64 return; 65 66 cpus = of_find_node_by_path("/cpus"); 67 if (!cpus) 68 return; 69 70 for_each_child_of_node(cpus, np) { 71 if (of_device_is_compatible(np, "arm,cortex-a15")) 72 has_a15 = true; 73 else if (of_device_is_compatible(np, "arm,cortex-a7")) 74 has_a7 = true; 75 } 76 77 if (of_machine_is_compatible("renesas,r8a7790")) 78 syscier = 0x013111ef; 79 else if (of_machine_is_compatible("renesas,r8a7791")) 80 syscier = 0x00111003; 81 82 /* RAM for jump stub, because BAR requires 256KB aligned address */ 83 p = ioremap_nocache(boot_vector_addr, shmobile_boot_size); 84 memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size); 85 iounmap(p); 86 87 /* setup reset vectors */ 88 p = ioremap_nocache(RST, 0x63); 89 bar = (boot_vector_addr >> 8) & 0xfffffc00; 90 if (has_a15) { 91 writel_relaxed(bar, p + CA15BAR); 92 writel_relaxed(bar | 0x10, p + CA15BAR); 93 94 /* de-assert reset for CA15 CPUs */ 95 writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) | 96 0xa5a50000, p + CA15RESCNT); 97 } 98 if (has_a7) { 99 writel_relaxed(bar, p + CA7BAR); 100 writel_relaxed(bar | 0x10, p + CA7BAR); 101 102 /* de-assert reset for CA7 CPUs */ 103 writel_relaxed((readl_relaxed(p + CA7RESCNT) & ~0x0f) | 104 0x5a5a0000, p + CA7RESCNT); 105 } 106 iounmap(p); 107 108 rcar_gen2_sysc_init(syscier); 109 shmobile_smp_apmu_suspend_init(); 110 } 111