1 /*
2  * R-Car Generation 2 Power management support
3  *
4  * Copyright (C) 2013 - 2015  Renesas Electronics Corporation
5  * Copyright (C) 2011  Renesas Solutions Corp.
6  * Copyright (C) 2011  Magnus Damm
7  *
8  * This file is subject to the terms and conditions of the GNU General Public
9  * License.  See the file "COPYING" in the main directory of this archive
10  * for more details.
11  */
12 
13 #include <linux/kernel.h>
14 #include <linux/of.h>
15 #include <linux/smp.h>
16 #include <linux/soc/renesas/rcar-sysc.h>
17 #include <asm/io.h>
18 #include "common.h"
19 #include "rcar-gen2.h"
20 
21 /* RST */
22 #define RST		0xe6160000
23 
24 #define CA15BAR		0x0020		/* CA15 Boot Address Register */
25 #define CA7BAR		0x0030		/* CA7 Boot Address Register */
26 #define CA15RESCNT	0x0040		/* CA15 Reset Control Register */
27 #define CA7RESCNT	0x0044		/* CA7 Reset Control Register */
28 
29 /* SYS Boot Address Register */
30 #define SBAR_BAREN	BIT(4)		/* SBAR is valid */
31 
32 /* Reset Control Registers */
33 #define CA15RESCNT_CODE	0xa5a50000
34 #define CA15RESCNT_CPUS	0xf		/* CPU0-3 */
35 #define CA7RESCNT_CODE	0x5a5a0000
36 #define CA7RESCNT_CPUS	0xf		/* CPU0-3 */
37 
38 
39 /* On-chip RAM */
40 #define ICRAM1		0xe63c0000	/* Inter Connect RAM1 (4 KiB) */
41 
42 static inline u32 phys_to_sbar(phys_addr_t addr)
43 {
44 	return (addr >> 8) & 0xfffffc00;
45 }
46 
47 /* SYSC */
48 #define SYSCIER 0x0c
49 #define SYSCIMR 0x10
50 
51 #if defined(CONFIG_SMP)
52 
53 static void __init rcar_gen2_sysc_init(u32 syscier)
54 {
55 	rcar_sysc_init(0xe6180000, syscier);
56 }
57 
58 #else /* CONFIG_SMP */
59 
60 static inline void rcar_gen2_sysc_init(u32 syscier) {}
61 
62 #endif /* CONFIG_SMP */
63 
64 void __init rcar_gen2_pm_init(void)
65 {
66 	void __iomem *p;
67 	u32 bar;
68 	static int once;
69 	struct device_node *np, *cpus;
70 	bool has_a7 = false;
71 	bool has_a15 = false;
72 	phys_addr_t boot_vector_addr = ICRAM1;
73 	u32 syscier = 0;
74 
75 	if (once++)
76 		return;
77 
78 	cpus = of_find_node_by_path("/cpus");
79 	if (!cpus)
80 		return;
81 
82 	for_each_child_of_node(cpus, np) {
83 		if (of_device_is_compatible(np, "arm,cortex-a15"))
84 			has_a15 = true;
85 		else if (of_device_is_compatible(np, "arm,cortex-a7"))
86 			has_a7 = true;
87 	}
88 
89 	if (of_machine_is_compatible("renesas,r8a7790"))
90 		syscier = 0x013111ef;
91 	else if (of_machine_is_compatible("renesas,r8a7791"))
92 		syscier = 0x00111003;
93 
94 	/* RAM for jump stub, because BAR requires 256KB aligned address */
95 	p = ioremap_nocache(boot_vector_addr, shmobile_boot_size);
96 	memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
97 	iounmap(p);
98 
99 	/* setup reset vectors */
100 	p = ioremap_nocache(RST, 0x63);
101 	bar = phys_to_sbar(boot_vector_addr);
102 	if (has_a15) {
103 		writel_relaxed(bar, p + CA15BAR);
104 		writel_relaxed(bar | SBAR_BAREN, p + CA15BAR);
105 
106 		/* de-assert reset for CA15 CPUs */
107 		writel_relaxed((readl_relaxed(p + CA15RESCNT) &
108 				~CA15RESCNT_CPUS) | CA15RESCNT_CODE,
109 			       p + CA15RESCNT);
110 	}
111 	if (has_a7) {
112 		writel_relaxed(bar, p + CA7BAR);
113 		writel_relaxed(bar | SBAR_BAREN, p + CA7BAR);
114 
115 		/* de-assert reset for CA7 CPUs */
116 		writel_relaxed((readl_relaxed(p + CA7RESCNT) &
117 				~CA7RESCNT_CPUS) | CA7RESCNT_CODE,
118 			       p + CA7RESCNT);
119 	}
120 	iounmap(p);
121 
122 	rcar_gen2_sysc_init(syscier);
123 	shmobile_smp_apmu_suspend_init();
124 }
125