1 /* 2 * SMP support for SoCs with APMU 3 * 4 * Copyright (C) 2014 Renesas Electronics Corporation 5 * Copyright (C) 2013 Magnus Damm 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <linux/cpu_pm.h> 12 #include <linux/delay.h> 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <linux/ioport.h> 16 #include <linux/of_address.h> 17 #include <linux/smp.h> 18 #include <linux/suspend.h> 19 #include <linux/threads.h> 20 #include <asm/cacheflush.h> 21 #include <asm/cp15.h> 22 #include <asm/proc-fns.h> 23 #include <asm/smp_plat.h> 24 #include <asm/suspend.h> 25 #include "common.h" 26 #include "platsmp-apmu.h" 27 28 static struct { 29 void __iomem *iomem; 30 int bit; 31 } apmu_cpus[NR_CPUS]; 32 33 #define WUPCR_OFFS 0x10 34 #define PSTR_OFFS 0x40 35 #define CPUNCR_OFFS(n) (0x100 + (0x10 * (n))) 36 37 static int __maybe_unused apmu_power_on(void __iomem *p, int bit) 38 { 39 /* request power on */ 40 writel_relaxed(BIT(bit), p + WUPCR_OFFS); 41 42 /* wait for APMU to finish */ 43 while (readl_relaxed(p + WUPCR_OFFS) != 0) 44 ; 45 46 return 0; 47 } 48 49 static int __maybe_unused apmu_power_off(void __iomem *p, int bit) 50 { 51 /* request Core Standby for next WFI */ 52 writel_relaxed(3, p + CPUNCR_OFFS(bit)); 53 return 0; 54 } 55 56 static int __maybe_unused apmu_power_off_poll(void __iomem *p, int bit) 57 { 58 int k; 59 60 for (k = 0; k < 1000; k++) { 61 if (((readl_relaxed(p + PSTR_OFFS) >> (bit * 4)) & 0x03) == 3) 62 return 1; 63 64 mdelay(1); 65 } 66 67 return 0; 68 } 69 70 static int __maybe_unused apmu_wrap(int cpu, int (*fn)(void __iomem *p, int cpu)) 71 { 72 void __iomem *p = apmu_cpus[cpu].iomem; 73 74 return p ? fn(p, apmu_cpus[cpu].bit) : -EINVAL; 75 } 76 77 static void apmu_init_cpu(struct resource *res, int cpu, int bit) 78 { 79 if ((cpu >= ARRAY_SIZE(apmu_cpus)) || apmu_cpus[cpu].iomem) 80 return; 81 82 apmu_cpus[cpu].iomem = ioremap_nocache(res->start, resource_size(res)); 83 apmu_cpus[cpu].bit = bit; 84 85 pr_debug("apmu ioremap %d %d %pr\n", cpu, bit, res); 86 } 87 88 static void apmu_parse_cfg(void (*fn)(struct resource *res, int cpu, int bit), 89 struct rcar_apmu_config *apmu_config, int num) 90 { 91 int id; 92 int k; 93 int bit, index; 94 bool is_allowed; 95 96 for (k = 0; k < num; k++) { 97 /* only enable the cluster that includes the boot CPU */ 98 is_allowed = false; 99 for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) { 100 id = apmu_config[k].cpus[bit]; 101 if (id >= 0) { 102 if (id == cpu_logical_map(0)) 103 is_allowed = true; 104 } 105 } 106 if (!is_allowed) 107 continue; 108 109 for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) { 110 id = apmu_config[k].cpus[bit]; 111 if (id >= 0) { 112 index = get_logical_index(id); 113 if (index >= 0) 114 fn(&apmu_config[k].iomem, index, bit); 115 } 116 } 117 } 118 } 119 120 void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus, 121 struct rcar_apmu_config *apmu_config, 122 int num) 123 { 124 /* install boot code shared by all CPUs */ 125 shmobile_boot_fn = virt_to_phys(shmobile_smp_boot); 126 shmobile_boot_arg = MPIDR_HWID_BITMASK; 127 128 /* perform per-cpu setup */ 129 apmu_parse_cfg(apmu_init_cpu, apmu_config, num); 130 } 131 132 #ifdef CONFIG_SMP 133 int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle) 134 { 135 /* For this particular CPU register boot vector */ 136 shmobile_smp_hook(cpu, virt_to_phys(secondary_startup), 0); 137 138 return apmu_wrap(cpu, apmu_power_on); 139 } 140 #endif 141 142 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_SUSPEND) 143 /* nicked from arch/arm/mach-exynos/hotplug.c */ 144 static inline void cpu_enter_lowpower_a15(void) 145 { 146 unsigned int v; 147 148 asm volatile( 149 " mrc p15, 0, %0, c1, c0, 0\n" 150 " bic %0, %0, %1\n" 151 " mcr p15, 0, %0, c1, c0, 0\n" 152 : "=&r" (v) 153 : "Ir" (CR_C) 154 : "cc"); 155 156 flush_cache_louis(); 157 158 asm volatile( 159 /* 160 * Turn off coherency 161 */ 162 " mrc p15, 0, %0, c1, c0, 1\n" 163 " bic %0, %0, %1\n" 164 " mcr p15, 0, %0, c1, c0, 1\n" 165 : "=&r" (v) 166 : "Ir" (0x40) 167 : "cc"); 168 169 isb(); 170 dsb(); 171 } 172 173 static void shmobile_smp_apmu_cpu_shutdown(unsigned int cpu) 174 { 175 176 /* Select next sleep mode using the APMU */ 177 apmu_wrap(cpu, apmu_power_off); 178 179 /* Do ARM specific CPU shutdown */ 180 cpu_enter_lowpower_a15(); 181 } 182 183 static inline void cpu_leave_lowpower(void) 184 { 185 unsigned int v; 186 187 asm volatile("mrc p15, 0, %0, c1, c0, 0\n" 188 " orr %0, %0, %1\n" 189 " mcr p15, 0, %0, c1, c0, 0\n" 190 " mrc p15, 0, %0, c1, c0, 1\n" 191 " orr %0, %0, %2\n" 192 " mcr p15, 0, %0, c1, c0, 1\n" 193 : "=&r" (v) 194 : "Ir" (CR_C), "Ir" (0x40) 195 : "cc"); 196 } 197 #endif 198 199 #if defined(CONFIG_HOTPLUG_CPU) 200 void shmobile_smp_apmu_cpu_die(unsigned int cpu) 201 { 202 /* For this particular CPU deregister boot vector */ 203 shmobile_smp_hook(cpu, 0, 0); 204 205 /* Shutdown CPU core */ 206 shmobile_smp_apmu_cpu_shutdown(cpu); 207 208 /* jump to shared mach-shmobile sleep / reset code */ 209 shmobile_smp_sleep(); 210 } 211 212 int shmobile_smp_apmu_cpu_kill(unsigned int cpu) 213 { 214 return apmu_wrap(cpu, apmu_power_off_poll); 215 } 216 #endif 217 218 #if defined(CONFIG_SUSPEND) 219 static int shmobile_smp_apmu_do_suspend(unsigned long cpu) 220 { 221 shmobile_smp_hook(cpu, virt_to_phys(cpu_resume), 0); 222 shmobile_smp_apmu_cpu_shutdown(cpu); 223 cpu_do_idle(); /* WFI selects Core Standby */ 224 return 1; 225 } 226 227 static int shmobile_smp_apmu_enter_suspend(suspend_state_t state) 228 { 229 cpu_suspend(smp_processor_id(), shmobile_smp_apmu_do_suspend); 230 cpu_leave_lowpower(); 231 return 0; 232 } 233 234 void __init shmobile_smp_apmu_suspend_init(void) 235 { 236 shmobile_suspend_ops.enter = shmobile_smp_apmu_enter_suspend; 237 } 238 #endif 239