1/* 2 * SA11x0 Assembler Sleep/WakeUp Management Routines 3 * 4 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License. 8 * 9 * History: 10 * 11 * 2001-02-06: Cliff Brake Initial code 12 * 13 * 2001-08-29: Nicolas Pitre Simplified. 14 * 15 * 2002-05-27: Nicolas Pitre Revisited, more cleanup and simplification. 16 * Storage is on the stack now. 17 */ 18 19#include <linux/linkage.h> 20#include <asm/assembler.h> 21#include <mach/hardware.h> 22 23 .text 24/* 25 * sa1100_cpu_suspend() 26 * 27 * Causes sa11x0 to enter sleep state 28 * 29 */ 30 31ENTRY(sa1100_cpu_suspend) 32 stmfd sp!, {r4 - r12, lr} @ save registers on stack 33 mov r1, r0 34 ldr r3, =sa1100_cpu_resume @ return function 35 bl cpu_suspend 36 37 @ disable clock switching 38 mcr p15, 0, r1, c15, c2, 2 39 40 @ Adjust memory timing before lowering CPU clock 41 @ Clock speed adjustment without changing memory timing makes 42 @ CPU hang in some cases 43 ldr r0, =MDREFR 44 ldr r1, [r0] 45 orr r1, r1, #MDREFR_K1DB2 46 str r1, [r0] 47 48 @ delay 90us and set CPU PLL to lowest speed 49 @ fixes resume problem on high speed SA1110 50 mov r0, #90 51 bl __udelay 52 ldr r0, =PPCR 53 mov r1, #0 54 str r1, [r0] 55 mov r0, #90 56 bl __udelay 57 58 /* 59 * SA1110 SDRAM controller workaround. register values: 60 * 61 * r0 = &MSC0 62 * r1 = &MSC1 63 * r2 = &MSC2 64 * r3 = MSC0 value 65 * r4 = MSC1 value 66 * r5 = MSC2 value 67 * r6 = &MDREFR 68 * r7 = first MDREFR value 69 * r8 = second MDREFR value 70 * r9 = &MDCNFG 71 * r10 = MDCNFG value 72 * r11 = third MDREFR value 73 * r12 = &PMCR 74 * r13 = PMCR value (1) 75 */ 76 77 ldr r0, =MSC0 78 ldr r1, =MSC1 79 ldr r2, =MSC2 80 81 ldr r3, [r0] 82 bic r3, r3, #FMsk(MSC_RT) 83 bic r3, r3, #FMsk(MSC_RT)<<16 84 85 ldr r4, [r1] 86 bic r4, r4, #FMsk(MSC_RT) 87 bic r4, r4, #FMsk(MSC_RT)<<16 88 89 ldr r5, [r2] 90 bic r5, r5, #FMsk(MSC_RT) 91 bic r5, r5, #FMsk(MSC_RT)<<16 92 93 ldr r6, =MDREFR 94 95 ldr r7, [r6] 96bic r7, r7, #0x0000FF00 97bic r7, r7, #0x000000F0 98orr r8, r7, #MDREFR_SLFRSH 99 100 ldr r9, =MDCNFG 101 ldr r10, [r9] 102 bic r10, r10, #(MDCNFG_DE0+MDCNFG_DE1) 103 bic r10, r10, #(MDCNFG_DE2+MDCNFG_DE3) 104 105 bic r11, r8, #MDREFR_SLFRSH 106 bic r11, r11, #MDREFR_E1PIN 107 108 ldr r12, =PMCR 109 110 mov r13, #PMCR_SF 111 112 b sa1110_sdram_controller_fix 113 114 .align 5 115sa1110_sdram_controller_fix: 116 117 @ Step 1 clear RT field of all MSCx registers 118 str r3, [r0] 119 str r4, [r1] 120 str r5, [r2] 121 122 @ Step 2 clear DRI field in MDREFR 123 str r7, [r6] 124 125 @ Step 3 set SLFRSH bit in MDREFR 126 str r8, [r6] 127 128 @ Step 4 clear DE bis in MDCNFG 129 str r10, [r9] 130 131 @ Step 5 clear DRAM refresh control register 132 str r11, [r6] 133 134 @ Wow, now the hardware suspend request pins can be used, that makes them functional for 135 @ about 7 ns out of the entire time that the CPU is running! 136 137 @ Step 6 set force sleep bit in PMCR 138 139 str r13, [r12] 140 14120: b 20b @ loop waiting for sleep 142 143/* 144 * cpu_sa1100_resume() 145 * 146 * entry point from bootloader into kernel during resume 147 */ 148 .align 5 149sa1100_cpu_resume: 150 mcr p15, 0, r1, c15, c1, 2 @ enable clock switching 151 ldmfd sp!, {r4 - r12, pc} @ return to caller 152