1/* 2 * SA11x0 Assembler Sleep/WakeUp Management Routines 3 * 4 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License. 8 * 9 * History: 10 * 11 * 2001-02-06: Cliff Brake Initial code 12 * 13 * 2001-08-29: Nicolas Pitre Simplified. 14 * 15 * 2002-05-27: Nicolas Pitre Revisited, more cleanup and simplification. 16 * Storage is on the stack now. 17 */ 18 19#include <linux/linkage.h> 20#include <asm/assembler.h> 21#include <mach/hardware.h> 22 23 .text 24/* 25 * sa1100_finish_suspend() 26 * 27 * Causes sa11x0 to enter sleep state 28 * 29 */ 30 31ENTRY(sa1100_finish_suspend) 32 @ disable clock switching 33 mcr p15, 0, r1, c15, c2, 2 34 35 @ Adjust memory timing before lowering CPU clock 36 @ Clock speed adjustment without changing memory timing makes 37 @ CPU hang in some cases 38 ldr r0, =MDREFR 39 ldr r1, [r0] 40 orr r1, r1, #MDREFR_K1DB2 41 str r1, [r0] 42 43 @ delay 90us and set CPU PLL to lowest speed 44 @ fixes resume problem on high speed SA1110 45 mov r0, #90 46 bl __udelay 47 ldr r0, =PPCR 48 mov r1, #0 49 str r1, [r0] 50 mov r0, #90 51 bl __udelay 52 53 /* 54 * SA1110 SDRAM controller workaround. register values: 55 * 56 * r0 = &MSC0 57 * r1 = &MSC1 58 * r2 = &MSC2 59 * r3 = MSC0 value 60 * r4 = MSC1 value 61 * r5 = MSC2 value 62 * r6 = &MDREFR 63 * r7 = first MDREFR value 64 * r8 = second MDREFR value 65 * r9 = &MDCNFG 66 * r10 = MDCNFG value 67 * r11 = third MDREFR value 68 * r12 = &PMCR 69 * r13 = PMCR value (1) 70 */ 71 72 ldr r0, =MSC0 73 ldr r1, =MSC1 74 ldr r2, =MSC2 75 76 ldr r3, [r0] 77 bic r3, r3, #FMsk(MSC_RT) 78 bic r3, r3, #FMsk(MSC_RT)<<16 79 80 ldr r4, [r1] 81 bic r4, r4, #FMsk(MSC_RT) 82 bic r4, r4, #FMsk(MSC_RT)<<16 83 84 ldr r5, [r2] 85 bic r5, r5, #FMsk(MSC_RT) 86 bic r5, r5, #FMsk(MSC_RT)<<16 87 88 ldr r6, =MDREFR 89 90 ldr r7, [r6] 91bic r7, r7, #0x0000FF00 92bic r7, r7, #0x000000F0 93orr r8, r7, #MDREFR_SLFRSH 94 95 ldr r9, =MDCNFG 96 ldr r10, [r9] 97 bic r10, r10, #(MDCNFG_DE0+MDCNFG_DE1) 98 bic r10, r10, #(MDCNFG_DE2+MDCNFG_DE3) 99 100 bic r11, r8, #MDREFR_SLFRSH 101 bic r11, r11, #MDREFR_E1PIN 102 103 ldr r12, =PMCR 104 105 mov r13, #PMCR_SF 106 107 b sa1110_sdram_controller_fix 108 109 .align 5 110sa1110_sdram_controller_fix: 111 112 @ Step 1 clear RT field of all MSCx registers 113 str r3, [r0] 114 str r4, [r1] 115 str r5, [r2] 116 117 @ Step 2 clear DRI field in MDREFR 118 str r7, [r6] 119 120 @ Step 3 set SLFRSH bit in MDREFR 121 str r8, [r6] 122 123 @ Step 4 clear DE bis in MDCNFG 124 str r10, [r9] 125 126 @ Step 5 clear DRAM refresh control register 127 str r11, [r6] 128 129 @ Wow, now the hardware suspend request pins can be used, that makes them functional for 130 @ about 7 ns out of the entire time that the CPU is running! 131 132 @ Step 6 set force sleep bit in PMCR 133 134 str r13, [r12] 135 13620: b 20b @ loop waiting for sleep 137