1 /* 2 * linux/arch/arm/mach-sa1100/jornada720.c 3 * 4 * HP Jornada720 init code 5 * 6 * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com> 7 * Copyright (C) 2006 Filip Zyzniewski <filip.zyzniewski@tefnet.pl> 8 * Copyright (C) 2005 Michael Gernoth <michael@gernoth.net> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 */ 15 16 #include <linux/init.h> 17 #include <linux/kernel.h> 18 #include <linux/tty.h> 19 #include <linux/delay.h> 20 #include <linux/platform_data/sa11x0-serial.h> 21 #include <linux/platform_device.h> 22 #include <linux/ioport.h> 23 #include <linux/mtd/mtd.h> 24 #include <linux/mtd/partitions.h> 25 #include <video/s1d13xxxfb.h> 26 27 #include <asm/hardware/sa1111.h> 28 #include <asm/page.h> 29 #include <asm/mach-types.h> 30 #include <asm/setup.h> 31 #include <asm/mach/arch.h> 32 #include <asm/mach/flash.h> 33 #include <asm/mach/map.h> 34 35 #include <mach/hardware.h> 36 #include <mach/irqs.h> 37 38 #include "generic.h" 39 40 /* 41 * HP Documentation referred in this file: 42 * http://www.jlime.com/downloads/development/docs/jornada7xx/jornada720.txt 43 */ 44 45 /* line 110 of HP's doc */ 46 #define TUCR_VAL 0x20000400 47 48 /* memory space (line 52 of HP's doc) */ 49 #define SA1111REGSTART 0x40000000 50 #define SA1111REGLEN 0x00002000 51 #define EPSONREGSTART 0x48000000 52 #define EPSONREGLEN 0x00100000 53 #define EPSONFBSTART 0x48200000 54 /* 512kB framebuffer */ 55 #define EPSONFBLEN 512*1024 56 57 static struct s1d13xxxfb_regval s1d13xxxfb_initregs[] = { 58 /* line 344 of HP's doc */ 59 {0x0001,0x00}, // Miscellaneous Register 60 {0x01FC,0x00}, // Display Mode Register 61 {0x0004,0x00}, // General IO Pins Configuration Register 0 62 {0x0005,0x00}, // General IO Pins Configuration Register 1 63 {0x0008,0x00}, // General IO Pins Control Register 0 64 {0x0009,0x00}, // General IO Pins Control Register 1 65 {0x0010,0x01}, // Memory Clock Configuration Register 66 {0x0014,0x11}, // LCD Pixel Clock Configuration Register 67 {0x0018,0x01}, // CRT/TV Pixel Clock Configuration Register 68 {0x001C,0x01}, // MediaPlug Clock Configuration Register 69 {0x001E,0x01}, // CPU To Memory Wait State Select Register 70 {0x0020,0x00}, // Memory Configuration Register 71 {0x0021,0x45}, // DRAM Refresh Rate Register 72 {0x002A,0x01}, // DRAM Timings Control Register 0 73 {0x002B,0x03}, // DRAM Timings Control Register 1 74 {0x0030,0x1c}, // Panel Type Register 75 {0x0031,0x00}, // MOD Rate Register 76 {0x0032,0x4F}, // LCD Horizontal Display Width Register 77 {0x0034,0x07}, // LCD Horizontal Non-Display Period Register 78 {0x0035,0x01}, // TFT FPLINE Start Position Register 79 {0x0036,0x0B}, // TFT FPLINE Pulse Width Register 80 {0x0038,0xEF}, // LCD Vertical Display Height Register 0 81 {0x0039,0x00}, // LCD Vertical Display Height Register 1 82 {0x003A,0x13}, // LCD Vertical Non-Display Period Register 83 {0x003B,0x0B}, // TFT FPFRAME Start Position Register 84 {0x003C,0x01}, // TFT FPFRAME Pulse Width Register 85 {0x0040,0x05}, // LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp) 86 {0x0041,0x00}, // LCD Miscellaneous Register 87 {0x0042,0x00}, // LCD Display Start Address Register 0 88 {0x0043,0x00}, // LCD Display Start Address Register 1 89 {0x0044,0x00}, // LCD Display Start Address Register 2 90 {0x0046,0x80}, // LCD Memory Address Offset Register 0 91 {0x0047,0x02}, // LCD Memory Address Offset Register 1 92 {0x0048,0x00}, // LCD Pixel Panning Register 93 {0x004A,0x00}, // LCD Display FIFO High Threshold Control Register 94 {0x004B,0x00}, // LCD Display FIFO Low Threshold Control Register 95 {0x0050,0x4F}, // CRT/TV Horizontal Display Width Register 96 {0x0052,0x13}, // CRT/TV Horizontal Non-Display Period Register 97 {0x0053,0x01}, // CRT/TV HRTC Start Position Register 98 {0x0054,0x0B}, // CRT/TV HRTC Pulse Width Register 99 {0x0056,0xDF}, // CRT/TV Vertical Display Height Register 0 100 {0x0057,0x01}, // CRT/TV Vertical Display Height Register 1 101 {0x0058,0x2B}, // CRT/TV Vertical Non-Display Period Register 102 {0x0059,0x09}, // CRT/TV VRTC Start Position Register 103 {0x005A,0x01}, // CRT/TV VRTC Pulse Width Register 104 {0x005B,0x10}, // TV Output Control Register 105 {0x0060,0x03}, // CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp) 106 {0x0062,0x00}, // CRT/TV Display Start Address Register 0 107 {0x0063,0x00}, // CRT/TV Display Start Address Register 1 108 {0x0064,0x00}, // CRT/TV Display Start Address Register 2 109 {0x0066,0x40}, // CRT/TV Memory Address Offset Register 0 110 {0x0067,0x01}, // CRT/TV Memory Address Offset Register 1 111 {0x0068,0x00}, // CRT/TV Pixel Panning Register 112 {0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register 113 {0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register 114 {0x0070,0x00}, // LCD Ink/Cursor Control Register 115 {0x0071,0x01}, // LCD Ink/Cursor Start Address Register 116 {0x0072,0x00}, // LCD Cursor X Position Register 0 117 {0x0073,0x00}, // LCD Cursor X Position Register 1 118 {0x0074,0x00}, // LCD Cursor Y Position Register 0 119 {0x0075,0x00}, // LCD Cursor Y Position Register 1 120 {0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register 121 {0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register 122 {0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register 123 {0x007A,0x1F}, // LCD Ink/Cursor Blue Color 1 Register 124 {0x007B,0x3F}, // LCD Ink/Cursor Green Color 1 Register 125 {0x007C,0x1F}, // LCD Ink/Cursor Red Color 1 Register 126 {0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register 127 {0x0080,0x00}, // CRT/TV Ink/Cursor Control Register 128 {0x0081,0x01}, // CRT/TV Ink/Cursor Start Address Register 129 {0x0082,0x00}, // CRT/TV Cursor X Position Register 0 130 {0x0083,0x00}, // CRT/TV Cursor X Position Register 1 131 {0x0084,0x00}, // CRT/TV Cursor Y Position Register 0 132 {0x0085,0x00}, // CRT/TV Cursor Y Position Register 1 133 {0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register 134 {0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register 135 {0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register 136 {0x008A,0x1F}, // CRT/TV Ink/Cursor Blue Color 1 Register 137 {0x008B,0x3F}, // CRT/TV Ink/Cursor Green Color 1 Register 138 {0x008C,0x1F}, // CRT/TV Ink/Cursor Red Color 1 Register 139 {0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register 140 {0x0100,0x00}, // BitBlt Control Register 0 141 {0x0101,0x00}, // BitBlt Control Register 1 142 {0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register 143 {0x0103,0x00}, // BitBlt Operation Register 144 {0x0104,0x00}, // BitBlt Source Start Address Register 0 145 {0x0105,0x00}, // BitBlt Source Start Address Register 1 146 {0x0106,0x00}, // BitBlt Source Start Address Register 2 147 {0x0108,0x00}, // BitBlt Destination Start Address Register 0 148 {0x0109,0x00}, // BitBlt Destination Start Address Register 1 149 {0x010A,0x00}, // BitBlt Destination Start Address Register 2 150 {0x010C,0x00}, // BitBlt Memory Address Offset Register 0 151 {0x010D,0x00}, // BitBlt Memory Address Offset Register 1 152 {0x0110,0x00}, // BitBlt Width Register 0 153 {0x0111,0x00}, // BitBlt Width Register 1 154 {0x0112,0x00}, // BitBlt Height Register 0 155 {0x0113,0x00}, // BitBlt Height Register 1 156 {0x0114,0x00}, // BitBlt Background Color Register 0 157 {0x0115,0x00}, // BitBlt Background Color Register 1 158 {0x0118,0x00}, // BitBlt Foreground Color Register 0 159 {0x0119,0x00}, // BitBlt Foreground Color Register 1 160 {0x01E0,0x00}, // Look-Up Table Mode Register 161 {0x01E2,0x00}, // Look-Up Table Address Register 162 /* not sure, wouldn't like to mess with the driver */ 163 {0x01E4,0x00}, // Look-Up Table Data Register 164 /* jornada doc says 0x00, but I trust the driver */ 165 {0x01F0,0x10}, // Power Save Configuration Register 166 {0x01F1,0x00}, // Power Save Status Register 167 {0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register 168 {0x01FC,0x01}, // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT) 169 }; 170 171 static struct s1d13xxxfb_pdata s1d13xxxfb_data = { 172 .initregs = s1d13xxxfb_initregs, 173 .initregssize = ARRAY_SIZE(s1d13xxxfb_initregs), 174 .platform_init_video = NULL 175 }; 176 177 static struct resource s1d13xxxfb_resources[] = { 178 [0] = DEFINE_RES_MEM(EPSONFBSTART, EPSONFBLEN), 179 [1] = DEFINE_RES_MEM(EPSONREGSTART, EPSONREGLEN), 180 }; 181 182 static struct platform_device s1d13xxxfb_device = { 183 .name = S1D_DEVICENAME, 184 .id = 0, 185 .dev = { 186 .platform_data = &s1d13xxxfb_data, 187 }, 188 .num_resources = ARRAY_SIZE(s1d13xxxfb_resources), 189 .resource = s1d13xxxfb_resources, 190 }; 191 192 static struct resource sa1111_resources[] = { 193 [0] = DEFINE_RES_MEM(SA1111REGSTART, SA1111REGLEN), 194 [1] = DEFINE_RES_IRQ(IRQ_GPIO1), 195 }; 196 197 static struct sa1111_platform_data sa1111_info = { 198 .disable_devs = SA1111_DEVID_PS2_MSE, 199 }; 200 201 static u64 sa1111_dmamask = 0xffffffffUL; 202 203 static struct platform_device sa1111_device = { 204 .name = "sa1111", 205 .id = 0, 206 .dev = { 207 .dma_mask = &sa1111_dmamask, 208 .coherent_dma_mask = 0xffffffff, 209 .platform_data = &sa1111_info, 210 }, 211 .num_resources = ARRAY_SIZE(sa1111_resources), 212 .resource = sa1111_resources, 213 }; 214 215 static struct platform_device jornada_ssp_device = { 216 .name = "jornada_ssp", 217 .id = -1, 218 }; 219 220 static struct platform_device jornada_kbd_device = { 221 .name = "jornada720_kbd", 222 .id = -1, 223 }; 224 225 static struct platform_device jornada_ts_device = { 226 .name = "jornada_ts", 227 .id = -1, 228 }; 229 230 static struct platform_device *devices[] __initdata = { 231 &sa1111_device, 232 &jornada_ssp_device, 233 &s1d13xxxfb_device, 234 &jornada_kbd_device, 235 &jornada_ts_device, 236 }; 237 238 static int __init jornada720_init(void) 239 { 240 int ret = -ENODEV; 241 242 if (machine_is_jornada720()) { 243 /* we want to use gpio20 as input to drive the clock of our uart 3 */ 244 GPDR |= GPIO_GPIO20; /* Clear gpio20 pin as input */ 245 TUCR = TUCR_VAL; 246 GPSR = GPIO_GPIO20; /* start gpio20 pin */ 247 udelay(1); 248 GPCR = GPIO_GPIO20; /* stop gpio20 */ 249 udelay(1); 250 GPSR = GPIO_GPIO20; /* restart gpio20 */ 251 udelay(20); /* give it some time to restart */ 252 253 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 254 } 255 256 return ret; 257 } 258 259 arch_initcall(jornada720_init); 260 261 static struct map_desc jornada720_io_desc[] __initdata = { 262 { /* Epson registers */ 263 .virtual = 0xf0000000, 264 .pfn = __phys_to_pfn(EPSONREGSTART), 265 .length = EPSONREGLEN, 266 .type = MT_DEVICE 267 }, { /* Epson frame buffer */ 268 .virtual = 0xf1000000, 269 .pfn = __phys_to_pfn(EPSONFBSTART), 270 .length = EPSONFBLEN, 271 .type = MT_DEVICE 272 } 273 }; 274 275 static void __init jornada720_map_io(void) 276 { 277 sa1100_map_io(); 278 iotable_init(jornada720_io_desc, ARRAY_SIZE(jornada720_io_desc)); 279 280 sa1100_register_uart(0, 3); 281 sa1100_register_uart(1, 1); 282 } 283 284 static struct mtd_partition jornada720_partitions[] = { 285 { 286 .name = "JORNADA720 boot firmware", 287 .size = 0x00040000, 288 .offset = 0, 289 .mask_flags = MTD_WRITEABLE, /* force read-only */ 290 }, { 291 .name = "JORNADA720 kernel", 292 .size = 0x000c0000, 293 .offset = 0x00040000, 294 }, { 295 .name = "JORNADA720 params", 296 .size = 0x00040000, 297 .offset = 0x00100000, 298 }, { 299 .name = "JORNADA720 initrd", 300 .size = 0x00100000, 301 .offset = 0x00140000, 302 }, { 303 .name = "JORNADA720 root cramfs", 304 .size = 0x00300000, 305 .offset = 0x00240000, 306 }, { 307 .name = "JORNADA720 usr cramfs", 308 .size = 0x00800000, 309 .offset = 0x00540000, 310 }, { 311 .name = "JORNADA720 usr local", 312 .size = 0, /* will expand to the end of the flash */ 313 .offset = 0x00d00000, 314 } 315 }; 316 317 static void jornada720_set_vpp(int vpp) 318 { 319 if (vpp) 320 /* enabling flash write (line 470 of HP's doc) */ 321 PPSR |= PPC_LDD7; 322 else 323 /* disabling flash write (line 470 of HP's doc) */ 324 PPSR &= ~PPC_LDD7; 325 PPDR |= PPC_LDD7; 326 } 327 328 static struct flash_platform_data jornada720_flash_data = { 329 .map_name = "cfi_probe", 330 .set_vpp = jornada720_set_vpp, 331 .parts = jornada720_partitions, 332 .nr_parts = ARRAY_SIZE(jornada720_partitions), 333 }; 334 335 static struct resource jornada720_flash_resource = 336 DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M); 337 338 static void __init jornada720_mach_init(void) 339 { 340 sa11x0_register_mtd(&jornada720_flash_data, &jornada720_flash_resource, 1); 341 } 342 343 MACHINE_START(JORNADA720, "HP Jornada 720") 344 /* Maintainer: Kristoffer Ericson <Kristoffer.Ericson@gmail.com> */ 345 .atag_offset = 0x100, 346 .map_io = jornada720_map_io, 347 .nr_irqs = SA1100_NR_IRQS, 348 .init_irq = sa1100_init_irq, 349 .init_time = sa1100_timer_init, 350 .init_machine = jornada720_mach_init, 351 .init_late = sa11x0_init_late, 352 #ifdef CONFIG_SA1111 353 .dma_zone_size = SZ_1M, 354 #endif 355 .restart = sa11x0_restart, 356 MACHINE_END 357