1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * linux/arch/arm/mach-sa1100/jornada720.c
4  *
5  * HP Jornada720 init code
6  *
7  * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
8  * Copyright (C) 2006 Filip Zyzniewski <filip.zyzniewski@tefnet.pl>
9  *  Copyright (C) 2005 Michael Gernoth <michael@gernoth.net>
10  */
11 
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/tty.h>
15 #include <linux/delay.h>
16 #include <linux/gpio/machine.h>
17 #include <linux/platform_data/sa11x0-serial.h>
18 #include <linux/platform_device.h>
19 #include <linux/ioport.h>
20 #include <linux/mtd/mtd.h>
21 #include <linux/mtd/partitions.h>
22 #include <video/s1d13xxxfb.h>
23 
24 #include <asm/hardware/sa1111.h>
25 #include <asm/page.h>
26 #include <asm/mach-types.h>
27 #include <asm/setup.h>
28 #include <asm/mach/arch.h>
29 #include <asm/mach/flash.h>
30 #include <asm/mach/map.h>
31 
32 #include <mach/hardware.h>
33 #include <mach/irqs.h>
34 
35 #include "generic.h"
36 
37 /*
38  * HP Documentation referred in this file:
39  * http://www.jlime.com/downloads/development/docs/jornada7xx/jornada720.txt
40  */
41 
42 /* line 110 of HP's doc */
43 #define TUCR_VAL	0x20000400
44 
45 /* memory space (line 52 of HP's doc) */
46 #define SA1111REGSTART	0x40000000
47 #define SA1111REGLEN	0x00002000
48 #define EPSONREGSTART	0x48000000
49 #define EPSONREGLEN	0x00100000
50 #define EPSONFBSTART	0x48200000
51 /* 512kB framebuffer */
52 #define EPSONFBLEN	512*1024
53 
54 static struct s1d13xxxfb_regval s1d13xxxfb_initregs[] = {
55 	/* line 344 of HP's doc */
56 	{0x0001,0x00},	// Miscellaneous Register
57 	{0x01FC,0x00},	// Display Mode Register
58 	{0x0004,0x00},	// General IO Pins Configuration Register 0
59 	{0x0005,0x00},	// General IO Pins Configuration Register 1
60 	{0x0008,0x00},	// General IO Pins Control Register 0
61 	{0x0009,0x00},	// General IO Pins Control Register 1
62 	{0x0010,0x01},	// Memory Clock Configuration Register
63 	{0x0014,0x11},	// LCD Pixel Clock Configuration Register
64 	{0x0018,0x01},	// CRT/TV Pixel Clock Configuration Register
65 	{0x001C,0x01},	// MediaPlug Clock Configuration Register
66 	{0x001E,0x01},	// CPU To Memory Wait State Select Register
67 	{0x0020,0x00},	// Memory Configuration Register
68 	{0x0021,0x45},	// DRAM Refresh Rate Register
69 	{0x002A,0x01},	// DRAM Timings Control Register 0
70 	{0x002B,0x03},	// DRAM Timings Control Register 1
71 	{0x0030,0x1c},	// Panel Type Register
72 	{0x0031,0x00},	// MOD Rate Register
73 	{0x0032,0x4F},	// LCD Horizontal Display Width Register
74 	{0x0034,0x07},	// LCD Horizontal Non-Display Period Register
75 	{0x0035,0x01},	// TFT FPLINE Start Position Register
76 	{0x0036,0x0B},	// TFT FPLINE Pulse Width Register
77 	{0x0038,0xEF},	// LCD Vertical Display Height Register 0
78 	{0x0039,0x00},	// LCD Vertical Display Height Register 1
79 	{0x003A,0x13},	// LCD Vertical Non-Display Period Register
80 	{0x003B,0x0B},	// TFT FPFRAME Start Position Register
81 	{0x003C,0x01},	// TFT FPFRAME Pulse Width Register
82 	{0x0040,0x05},	// LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
83 	{0x0041,0x00},	// LCD Miscellaneous Register
84 	{0x0042,0x00},	// LCD Display Start Address Register 0
85 	{0x0043,0x00},	// LCD Display Start Address Register 1
86 	{0x0044,0x00},	// LCD Display Start Address Register 2
87 	{0x0046,0x80},	// LCD Memory Address Offset Register 0
88 	{0x0047,0x02},	// LCD Memory Address Offset Register 1
89 	{0x0048,0x00},	// LCD Pixel Panning Register
90 	{0x004A,0x00},	// LCD Display FIFO High Threshold Control Register
91 	{0x004B,0x00},	// LCD Display FIFO Low Threshold Control Register
92 	{0x0050,0x4F},	// CRT/TV Horizontal Display Width Register
93 	{0x0052,0x13},	// CRT/TV Horizontal Non-Display Period Register
94 	{0x0053,0x01},	// CRT/TV HRTC Start Position Register
95 	{0x0054,0x0B},	// CRT/TV HRTC Pulse Width Register
96 	{0x0056,0xDF},	// CRT/TV Vertical Display Height Register 0
97 	{0x0057,0x01},	// CRT/TV Vertical Display Height Register 1
98 	{0x0058,0x2B},	// CRT/TV Vertical Non-Display Period Register
99 	{0x0059,0x09},	// CRT/TV VRTC Start Position Register
100 	{0x005A,0x01},	// CRT/TV VRTC Pulse Width Register
101 	{0x005B,0x10},	// TV Output Control Register
102 	{0x0060,0x03},	// CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
103 	{0x0062,0x00},	// CRT/TV Display Start Address Register 0
104 	{0x0063,0x00},	// CRT/TV Display Start Address Register 1
105 	{0x0064,0x00},	// CRT/TV Display Start Address Register 2
106 	{0x0066,0x40},	// CRT/TV Memory Address Offset Register 0
107 	{0x0067,0x01},	// CRT/TV Memory Address Offset Register 1
108 	{0x0068,0x00},	// CRT/TV Pixel Panning Register
109 	{0x006A,0x00},	// CRT/TV Display FIFO High Threshold Control Register
110 	{0x006B,0x00},	// CRT/TV Display FIFO Low Threshold Control Register
111 	{0x0070,0x00},	// LCD Ink/Cursor Control Register
112 	{0x0071,0x01},	// LCD Ink/Cursor Start Address Register
113 	{0x0072,0x00},	// LCD Cursor X Position Register 0
114 	{0x0073,0x00},	// LCD Cursor X Position Register 1
115 	{0x0074,0x00},	// LCD Cursor Y Position Register 0
116 	{0x0075,0x00},	// LCD Cursor Y Position Register 1
117 	{0x0076,0x00},	// LCD Ink/Cursor Blue Color 0 Register
118 	{0x0077,0x00},	// LCD Ink/Cursor Green Color 0 Register
119 	{0x0078,0x00},	// LCD Ink/Cursor Red Color 0 Register
120 	{0x007A,0x1F},	// LCD Ink/Cursor Blue Color 1 Register
121 	{0x007B,0x3F},	// LCD Ink/Cursor Green Color 1 Register
122 	{0x007C,0x1F},	// LCD Ink/Cursor Red Color 1 Register
123 	{0x007E,0x00},	// LCD Ink/Cursor FIFO Threshold Register
124 	{0x0080,0x00},	// CRT/TV Ink/Cursor Control Register
125 	{0x0081,0x01},	// CRT/TV Ink/Cursor Start Address Register
126 	{0x0082,0x00},	// CRT/TV Cursor X Position Register 0
127 	{0x0083,0x00},	// CRT/TV Cursor X Position Register 1
128 	{0x0084,0x00},	// CRT/TV Cursor Y Position Register 0
129 	{0x0085,0x00},	// CRT/TV Cursor Y Position Register 1
130 	{0x0086,0x00},	// CRT/TV Ink/Cursor Blue Color 0 Register
131 	{0x0087,0x00},	// CRT/TV Ink/Cursor Green Color 0 Register
132 	{0x0088,0x00},	// CRT/TV Ink/Cursor Red Color 0 Register
133 	{0x008A,0x1F},	// CRT/TV Ink/Cursor Blue Color 1 Register
134 	{0x008B,0x3F},	// CRT/TV Ink/Cursor Green Color 1 Register
135 	{0x008C,0x1F},	// CRT/TV Ink/Cursor Red Color 1 Register
136 	{0x008E,0x00},	// CRT/TV Ink/Cursor FIFO Threshold Register
137 	{0x0100,0x00},	// BitBlt Control Register 0
138 	{0x0101,0x00},	// BitBlt Control Register 1
139 	{0x0102,0x00},	// BitBlt ROP Code/Color Expansion Register
140 	{0x0103,0x00},	// BitBlt Operation Register
141 	{0x0104,0x00},	// BitBlt Source Start Address Register 0
142 	{0x0105,0x00},	// BitBlt Source Start Address Register 1
143 	{0x0106,0x00},	// BitBlt Source Start Address Register 2
144 	{0x0108,0x00},	// BitBlt Destination Start Address Register 0
145 	{0x0109,0x00},	// BitBlt Destination Start Address Register 1
146 	{0x010A,0x00},	// BitBlt Destination Start Address Register 2
147 	{0x010C,0x00},	// BitBlt Memory Address Offset Register 0
148 	{0x010D,0x00},	// BitBlt Memory Address Offset Register 1
149 	{0x0110,0x00},	// BitBlt Width Register 0
150 	{0x0111,0x00},	// BitBlt Width Register 1
151 	{0x0112,0x00},	// BitBlt Height Register 0
152 	{0x0113,0x00},	// BitBlt Height Register 1
153 	{0x0114,0x00},	// BitBlt Background Color Register 0
154 	{0x0115,0x00},	// BitBlt Background Color Register 1
155 	{0x0118,0x00},	// BitBlt Foreground Color Register 0
156 	{0x0119,0x00},	// BitBlt Foreground Color Register 1
157 	{0x01E0,0x00},	// Look-Up Table Mode Register
158 	{0x01E2,0x00},	// Look-Up Table Address Register
159 	/* not sure, wouldn't like to mess with the driver */
160 	{0x01E4,0x00},	// Look-Up Table Data Register
161 	/* jornada doc says 0x00, but I trust the driver */
162 	{0x01F0,0x10},	// Power Save Configuration Register
163 	{0x01F1,0x00},	// Power Save Status Register
164 	{0x01F4,0x00},	// CPU-to-Memory Access Watchdog Timer Register
165 	{0x01FC,0x01},	// Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT)
166 };
167 
168 static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
169 	.initregs		= s1d13xxxfb_initregs,
170 	.initregssize		= ARRAY_SIZE(s1d13xxxfb_initregs),
171 	.platform_init_video	= NULL
172 };
173 
174 static struct resource s1d13xxxfb_resources[] = {
175 	[0] = DEFINE_RES_MEM(EPSONFBSTART, EPSONFBLEN),
176 	[1] = DEFINE_RES_MEM(EPSONREGSTART, EPSONREGLEN),
177 };
178 
179 static struct platform_device s1d13xxxfb_device = {
180 	.name		= S1D_DEVICENAME,
181 	.id		= 0,
182 	.dev		= {
183 		.platform_data	= &s1d13xxxfb_data,
184 	},
185 	.num_resources	= ARRAY_SIZE(s1d13xxxfb_resources),
186 	.resource	= s1d13xxxfb_resources,
187 };
188 
189 static struct gpiod_lookup_table jornada_pcmcia_gpiod_table = {
190 	.dev_id = "1800",
191 	.table = {
192 		GPIO_LOOKUP("sa1111", 0, "s0-power", GPIO_ACTIVE_HIGH),
193 		GPIO_LOOKUP("sa1111", 1, "s1-power", GPIO_ACTIVE_HIGH),
194 		GPIO_LOOKUP("sa1111", 2, "s0-3v", GPIO_ACTIVE_HIGH),
195 		GPIO_LOOKUP("sa1111", 3, "s1-3v", GPIO_ACTIVE_HIGH),
196 		{ },
197 	},
198 };
199 
200 static struct resource sa1111_resources[] = {
201 	[0] = DEFINE_RES_MEM(SA1111REGSTART, SA1111REGLEN),
202 	[1] = DEFINE_RES_IRQ(IRQ_GPIO1),
203 };
204 
205 static struct sa1111_platform_data sa1111_info = {
206 	.disable_devs	= SA1111_DEVID_PS2_MSE,
207 };
208 
209 static u64 sa1111_dmamask = 0xffffffffUL;
210 
211 static struct platform_device sa1111_device = {
212 	.name		= "sa1111",
213 	.id		= 0,
214 	.dev		= {
215 		.dma_mask = &sa1111_dmamask,
216 		.coherent_dma_mask = 0xffffffff,
217 		.platform_data = &sa1111_info,
218 	},
219 	.num_resources	= ARRAY_SIZE(sa1111_resources),
220 	.resource	= sa1111_resources,
221 };
222 
223 static struct platform_device jornada_ssp_device = {
224 	.name           = "jornada_ssp",
225 	.id             = -1,
226 };
227 
228 static struct resource jornada_kbd_resources[] = {
229 	DEFINE_RES_IRQ(IRQ_GPIO0),
230 };
231 
232 static struct platform_device jornada_kbd_device = {
233 	.name		= "jornada720_kbd",
234 	.id		= -1,
235 	.num_resources	= ARRAY_SIZE(jornada_kbd_resources),
236 	.resource	= jornada_kbd_resources,
237 };
238 
239 static struct gpiod_lookup_table jornada_ts_gpiod_table = {
240 	.dev_id		= "jornada_ts",
241 	.table		= {
242 		GPIO_LOOKUP("gpio", 9, "penup", GPIO_ACTIVE_HIGH),
243 	},
244 };
245 
246 static struct platform_device jornada_ts_device = {
247 	.name		= "jornada_ts",
248 	.id		= -1,
249 };
250 
251 static struct platform_device *devices[] __initdata = {
252 	&sa1111_device,
253 	&jornada_ssp_device,
254 	&s1d13xxxfb_device,
255 	&jornada_kbd_device,
256 	&jornada_ts_device,
257 };
258 
259 static int __init jornada720_init(void)
260 {
261 	int ret = -ENODEV;
262 
263 	if (machine_is_jornada720()) {
264 		/* we want to use gpio20 as input to drive the clock of our uart 3 */
265 		GPDR |= GPIO_GPIO20;	/* Clear gpio20 pin as input */
266 		TUCR = TUCR_VAL;
267 		GPSR = GPIO_GPIO20;	/* start gpio20 pin */
268 		udelay(1);
269 		GPCR = GPIO_GPIO20;	/* stop gpio20 */
270 		udelay(1);
271 		GPSR = GPIO_GPIO20;	/* restart gpio20 */
272 		udelay(20);		/* give it some time to restart */
273 
274 		gpiod_add_lookup_table(&jornada_ts_gpiod_table);
275 		gpiod_add_lookup_table(&jornada_pcmcia_gpiod_table);
276 
277 		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
278 	}
279 
280 	return ret;
281 }
282 
283 arch_initcall(jornada720_init);
284 
285 static struct map_desc jornada720_io_desc[] __initdata = {
286 	{	/* Epson registers */
287 		.virtual	= 0xf0000000,
288 		.pfn		= __phys_to_pfn(EPSONREGSTART),
289 		.length		= EPSONREGLEN,
290 		.type		= MT_DEVICE
291 	}, {	/* Epson frame buffer */
292 		.virtual	= 0xf1000000,
293 		.pfn		= __phys_to_pfn(EPSONFBSTART),
294 		.length		= EPSONFBLEN,
295 		.type		= MT_DEVICE
296 	}
297 };
298 
299 static void __init jornada720_map_io(void)
300 {
301 	sa1100_map_io();
302 	iotable_init(jornada720_io_desc, ARRAY_SIZE(jornada720_io_desc));
303 
304 	sa1100_register_uart(0, 3);
305 	sa1100_register_uart(1, 1);
306 }
307 
308 static struct mtd_partition jornada720_partitions[] = {
309 	{
310 		.name		= "JORNADA720 boot firmware",
311 		.size		= 0x00040000,
312 		.offset		= 0,
313 		.mask_flags	= MTD_WRITEABLE, /* force read-only */
314 	}, {
315 		.name		= "JORNADA720 kernel",
316 		.size		= 0x000c0000,
317 		.offset		= 0x00040000,
318 	}, {
319 		.name		= "JORNADA720 params",
320 		.size		= 0x00040000,
321 		.offset		= 0x00100000,
322 	}, {
323 		.name		= "JORNADA720 initrd",
324 		.size		= 0x00100000,
325 		.offset		= 0x00140000,
326 	}, {
327 		.name		= "JORNADA720 root cramfs",
328 		.size		= 0x00300000,
329 		.offset		= 0x00240000,
330 	}, {
331 		.name		= "JORNADA720 usr cramfs",
332 		.size		= 0x00800000,
333 		.offset		= 0x00540000,
334 	}, {
335 		.name		= "JORNADA720 usr local",
336 		.size		= 0, /* will expand to the end of the flash */
337 		.offset		= 0x00d00000,
338 	}
339 };
340 
341 static void jornada720_set_vpp(int vpp)
342 {
343 	if (vpp)
344 		/* enabling flash write (line 470 of HP's doc) */
345 		PPSR |= PPC_LDD7;
346 	else
347 		/* disabling flash write (line 470 of HP's doc) */
348 		PPSR &= ~PPC_LDD7;
349 	PPDR |= PPC_LDD7;
350 }
351 
352 static struct flash_platform_data jornada720_flash_data = {
353 	.map_name	= "cfi_probe",
354 	.set_vpp	= jornada720_set_vpp,
355 	.parts		= jornada720_partitions,
356 	.nr_parts	= ARRAY_SIZE(jornada720_partitions),
357 };
358 
359 static struct resource jornada720_flash_resource =
360 	DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M);
361 
362 static void __init jornada720_mach_init(void)
363 {
364 	sa11x0_register_mtd(&jornada720_flash_data, &jornada720_flash_resource, 1);
365 }
366 
367 MACHINE_START(JORNADA720, "HP Jornada 720")
368 	/* Maintainer: Kristoffer Ericson <Kristoffer.Ericson@gmail.com> */
369 	.atag_offset	= 0x100,
370 	.map_io		= jornada720_map_io,
371 	.nr_irqs	= SA1100_NR_IRQS,
372 	.init_irq	= sa1100_init_irq,
373 	.init_time	= sa1100_timer_init,
374 	.init_machine	= jornada720_mach_init,
375 	.init_late	= sa11x0_init_late,
376 #ifdef CONFIG_SA1111
377 	.dma_zone_size	= SZ_1M,
378 #endif
379 	.restart	= sa11x0_restart,
380 MACHINE_END
381