1 /* 2 * arch/arm/mach-sa1100/include/mach/irqs.h 3 * 4 * Copyright (C) 1996 Russell King 5 * Copyright (C) 1998 Deborah Wallach (updates for SA1100/Brutus). 6 * Copyright (C) 1999 Nicolas Pitre (full GPIO irq isolation) 7 * 8 * 2001/11/14 RMK Cleaned up and standardised a lot of the IRQs. 9 */ 10 11 #define IRQ_GPIO0 1 12 #define IRQ_GPIO1 2 13 #define IRQ_GPIO2 3 14 #define IRQ_GPIO3 4 15 #define IRQ_GPIO4 5 16 #define IRQ_GPIO5 6 17 #define IRQ_GPIO6 7 18 #define IRQ_GPIO7 8 19 #define IRQ_GPIO8 9 20 #define IRQ_GPIO9 10 21 #define IRQ_GPIO10 11 22 #define IRQ_GPIO11_27 12 23 #define IRQ_LCD 13 /* LCD controller */ 24 #define IRQ_Ser0UDC 14 /* Ser. port 0 UDC */ 25 #define IRQ_Ser1SDLC 15 /* Ser. port 1 SDLC */ 26 #define IRQ_Ser1UART 16 /* Ser. port 1 UART */ 27 #define IRQ_Ser2ICP 17 /* Ser. port 2 ICP */ 28 #define IRQ_Ser3UART 18 /* Ser. port 3 UART */ 29 #define IRQ_Ser4MCP 19 /* Ser. port 4 MCP */ 30 #define IRQ_Ser4SSP 20 /* Ser. port 4 SSP */ 31 #define IRQ_DMA0 21 /* DMA controller channel 0 */ 32 #define IRQ_DMA1 22 /* DMA controller channel 1 */ 33 #define IRQ_DMA2 23 /* DMA controller channel 2 */ 34 #define IRQ_DMA3 24 /* DMA controller channel 3 */ 35 #define IRQ_DMA4 25 /* DMA controller channel 4 */ 36 #define IRQ_DMA5 26 /* DMA controller channel 5 */ 37 #define IRQ_OST0 27 /* OS Timer match 0 */ 38 #define IRQ_OST1 28 /* OS Timer match 1 */ 39 #define IRQ_OST2 29 /* OS Timer match 2 */ 40 #define IRQ_OST3 30 /* OS Timer match 3 */ 41 #define IRQ_RTC1Hz 31 /* RTC 1 Hz clock */ 42 #define IRQ_RTCAlrm 32 /* RTC Alarm */ 43 44 #define IRQ_GPIO11 33 45 #define IRQ_GPIO12 34 46 #define IRQ_GPIO13 35 47 #define IRQ_GPIO14 36 48 #define IRQ_GPIO15 37 49 #define IRQ_GPIO16 38 50 #define IRQ_GPIO17 39 51 #define IRQ_GPIO18 40 52 #define IRQ_GPIO19 41 53 #define IRQ_GPIO20 42 54 #define IRQ_GPIO21 43 55 #define IRQ_GPIO22 44 56 #define IRQ_GPIO23 45 57 #define IRQ_GPIO24 46 58 #define IRQ_GPIO25 47 59 #define IRQ_GPIO26 48 60 #define IRQ_GPIO27 49 61 62 /* 63 * The next 16 interrupts are for board specific purposes. Since 64 * the kernel can only run on one machine at a time, we can re-use 65 * these. If you need more, increase IRQ_BOARD_END, but keep it 66 * within sensible limits. IRQs 49 to 64 are available. 67 */ 68 #define IRQ_BOARD_START 50 69 #define IRQ_BOARD_END 66 70 71 /* 72 * Figure out the MAX IRQ number. 73 * 74 * Neponset, SA1111 and UCB1x00 are sparse IRQ aware, so can dynamically 75 * allocate their IRQs above NR_IRQS. 76 * 77 * LoCoMo has 4 additional IRQs, but is not sparse IRQ aware, and so has 78 * to be included in the NR_IRQS calculation. 79 */ 80 #ifdef CONFIG_SHARP_LOCOMO 81 #define NR_IRQS_LOCOMO 4 82 #else 83 #define NR_IRQS_LOCOMO 0 84 #endif 85 86 #ifndef NR_IRQS 87 #define NR_IRQS (IRQ_BOARD_START + NR_IRQS_LOCOMO) 88 #endif 89 #define SA1100_NR_IRQS (IRQ_BOARD_START + NR_IRQS_LOCOMO) 90