1 /* 2 * linux/arch/arm/mach-sa1100/generic.c 3 * 4 * Author: Nicolas Pitre 5 * 6 * Code common to all SA11x0 machines. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 #include <linux/gpio.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/init.h> 16 #include <linux/delay.h> 17 #include <linux/pm.h> 18 #include <linux/cpufreq.h> 19 #include <linux/ioport.h> 20 #include <linux/platform_device.h> 21 22 #include <video/sa1100fb.h> 23 24 #include <asm/div64.h> 25 #include <mach/hardware.h> 26 #include <asm/system.h> 27 #include <asm/mach/map.h> 28 #include <asm/mach/flash.h> 29 #include <asm/irq.h> 30 31 #include "generic.h" 32 33 unsigned int reset_status; 34 EXPORT_SYMBOL(reset_status); 35 36 #define NR_FREQS 16 37 38 /* 39 * This table is setup for a 3.6864MHz Crystal. 40 */ 41 static const unsigned short cclk_frequency_100khz[NR_FREQS] = { 42 590, /* 59.0 MHz */ 43 737, /* 73.7 MHz */ 44 885, /* 88.5 MHz */ 45 1032, /* 103.2 MHz */ 46 1180, /* 118.0 MHz */ 47 1327, /* 132.7 MHz */ 48 1475, /* 147.5 MHz */ 49 1622, /* 162.2 MHz */ 50 1769, /* 176.9 MHz */ 51 1917, /* 191.7 MHz */ 52 2064, /* 206.4 MHz */ 53 2212, /* 221.2 MHz */ 54 2359, /* 235.9 MHz */ 55 2507, /* 250.7 MHz */ 56 2654, /* 265.4 MHz */ 57 2802 /* 280.2 MHz */ 58 }; 59 60 /* rounds up(!) */ 61 unsigned int sa11x0_freq_to_ppcr(unsigned int khz) 62 { 63 int i; 64 65 khz /= 100; 66 67 for (i = 0; i < NR_FREQS; i++) 68 if (cclk_frequency_100khz[i] >= khz) 69 break; 70 71 return i; 72 } 73 74 unsigned int sa11x0_ppcr_to_freq(unsigned int idx) 75 { 76 unsigned int freq = 0; 77 if (idx < NR_FREQS) 78 freq = cclk_frequency_100khz[idx] * 100; 79 return freq; 80 } 81 82 83 /* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on 84 * this platform, anyway. 85 */ 86 int sa11x0_verify_speed(struct cpufreq_policy *policy) 87 { 88 unsigned int tmp; 89 if (policy->cpu) 90 return -EINVAL; 91 92 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq); 93 94 /* make sure that at least one frequency is within the policy */ 95 tmp = cclk_frequency_100khz[sa11x0_freq_to_ppcr(policy->min)] * 100; 96 if (tmp > policy->max) 97 policy->max = tmp; 98 99 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq); 100 101 return 0; 102 } 103 104 unsigned int sa11x0_getspeed(unsigned int cpu) 105 { 106 if (cpu) 107 return 0; 108 return cclk_frequency_100khz[PPCR & 0xf] * 100; 109 } 110 111 /* 112 * Default power-off for SA1100 113 */ 114 static void sa1100_power_off(void) 115 { 116 mdelay(100); 117 local_irq_disable(); 118 /* disable internal oscillator, float CS lines */ 119 PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS); 120 /* enable wake-up on GPIO0 (Assabet...) */ 121 PWER = GFER = GRER = 1; 122 /* 123 * set scratchpad to zero, just in case it is used as a 124 * restart address by the bootloader. 125 */ 126 PSPR = 0; 127 /* enter sleep mode */ 128 PMCR = PMCR_SF; 129 } 130 131 void sa11x0_restart(char mode, const char *cmd) 132 { 133 if (mode == 's') { 134 /* Jump into ROM at address 0 */ 135 soft_restart(0); 136 } else { 137 /* Use on-chip reset capability */ 138 RSRR = RSRR_SWR; 139 } 140 } 141 142 static void sa11x0_register_device(struct platform_device *dev, void *data) 143 { 144 int err; 145 dev->dev.platform_data = data; 146 err = platform_device_register(dev); 147 if (err) 148 printk(KERN_ERR "Unable to register device %s: %d\n", 149 dev->name, err); 150 } 151 152 153 static struct resource sa11x0udc_resources[] = { 154 [0] = { 155 .start = __PREG(Ser0UDCCR), 156 .end = __PREG(Ser0UDCCR) + 0xffff, 157 .flags = IORESOURCE_MEM, 158 }, 159 [1] = { 160 .start = IRQ_Ser0UDC, 161 .end = IRQ_Ser0UDC, 162 .flags = IORESOURCE_IRQ, 163 }, 164 }; 165 166 static u64 sa11x0udc_dma_mask = 0xffffffffUL; 167 168 static struct platform_device sa11x0udc_device = { 169 .name = "sa11x0-udc", 170 .id = -1, 171 .dev = { 172 .dma_mask = &sa11x0udc_dma_mask, 173 .coherent_dma_mask = 0xffffffff, 174 }, 175 .num_resources = ARRAY_SIZE(sa11x0udc_resources), 176 .resource = sa11x0udc_resources, 177 }; 178 179 static struct resource sa11x0uart1_resources[] = { 180 [0] = { 181 .start = __PREG(Ser1UTCR0), 182 .end = __PREG(Ser1UTCR0) + 0xffff, 183 .flags = IORESOURCE_MEM, 184 }, 185 [1] = { 186 .start = IRQ_Ser1UART, 187 .end = IRQ_Ser1UART, 188 .flags = IORESOURCE_IRQ, 189 }, 190 }; 191 192 static struct platform_device sa11x0uart1_device = { 193 .name = "sa11x0-uart", 194 .id = 1, 195 .num_resources = ARRAY_SIZE(sa11x0uart1_resources), 196 .resource = sa11x0uart1_resources, 197 }; 198 199 static struct resource sa11x0uart3_resources[] = { 200 [0] = { 201 .start = __PREG(Ser3UTCR0), 202 .end = __PREG(Ser3UTCR0) + 0xffff, 203 .flags = IORESOURCE_MEM, 204 }, 205 [1] = { 206 .start = IRQ_Ser3UART, 207 .end = IRQ_Ser3UART, 208 .flags = IORESOURCE_IRQ, 209 }, 210 }; 211 212 static struct platform_device sa11x0uart3_device = { 213 .name = "sa11x0-uart", 214 .id = 3, 215 .num_resources = ARRAY_SIZE(sa11x0uart3_resources), 216 .resource = sa11x0uart3_resources, 217 }; 218 219 static struct resource sa11x0mcp_resources[] = { 220 [0] = { 221 .start = __PREG(Ser4MCCR0), 222 .end = __PREG(Ser4MCCR0) + 0xffff, 223 .flags = IORESOURCE_MEM, 224 }, 225 [1] = { 226 .start = IRQ_Ser4MCP, 227 .end = IRQ_Ser4MCP, 228 .flags = IORESOURCE_IRQ, 229 }, 230 }; 231 232 static u64 sa11x0mcp_dma_mask = 0xffffffffUL; 233 234 static struct platform_device sa11x0mcp_device = { 235 .name = "sa11x0-mcp", 236 .id = -1, 237 .dev = { 238 .dma_mask = &sa11x0mcp_dma_mask, 239 .coherent_dma_mask = 0xffffffff, 240 }, 241 .num_resources = ARRAY_SIZE(sa11x0mcp_resources), 242 .resource = sa11x0mcp_resources, 243 }; 244 245 void sa11x0_register_mcp(struct mcp_plat_data *data) 246 { 247 sa11x0_register_device(&sa11x0mcp_device, data); 248 } 249 250 static struct resource sa11x0ssp_resources[] = { 251 [0] = { 252 .start = 0x80070000, 253 .end = 0x8007ffff, 254 .flags = IORESOURCE_MEM, 255 }, 256 [1] = { 257 .start = IRQ_Ser4SSP, 258 .end = IRQ_Ser4SSP, 259 .flags = IORESOURCE_IRQ, 260 }, 261 }; 262 263 static u64 sa11x0ssp_dma_mask = 0xffffffffUL; 264 265 static struct platform_device sa11x0ssp_device = { 266 .name = "sa11x0-ssp", 267 .id = -1, 268 .dev = { 269 .dma_mask = &sa11x0ssp_dma_mask, 270 .coherent_dma_mask = 0xffffffff, 271 }, 272 .num_resources = ARRAY_SIZE(sa11x0ssp_resources), 273 .resource = sa11x0ssp_resources, 274 }; 275 276 static struct resource sa11x0fb_resources[] = { 277 [0] = { 278 .start = 0xb0100000, 279 .end = 0xb010ffff, 280 .flags = IORESOURCE_MEM, 281 }, 282 [1] = { 283 .start = IRQ_LCD, 284 .end = IRQ_LCD, 285 .flags = IORESOURCE_IRQ, 286 }, 287 }; 288 289 static struct platform_device sa11x0fb_device = { 290 .name = "sa11x0-fb", 291 .id = -1, 292 .dev = { 293 .coherent_dma_mask = 0xffffffff, 294 }, 295 .num_resources = ARRAY_SIZE(sa11x0fb_resources), 296 .resource = sa11x0fb_resources, 297 }; 298 299 void sa11x0_register_lcd(struct sa1100fb_mach_info *inf) 300 { 301 sa11x0_register_device(&sa11x0fb_device, inf); 302 } 303 304 static struct platform_device sa11x0pcmcia_device = { 305 .name = "sa11x0-pcmcia", 306 .id = -1, 307 }; 308 309 static struct platform_device sa11x0mtd_device = { 310 .name = "sa1100-mtd", 311 .id = -1, 312 }; 313 314 void sa11x0_register_mtd(struct flash_platform_data *flash, 315 struct resource *res, int nr) 316 { 317 flash->name = "sa1100"; 318 sa11x0mtd_device.resource = res; 319 sa11x0mtd_device.num_resources = nr; 320 sa11x0_register_device(&sa11x0mtd_device, flash); 321 } 322 323 static struct resource sa11x0ir_resources[] = { 324 { 325 .start = __PREG(Ser2UTCR0), 326 .end = __PREG(Ser2UTCR0) + 0x24 - 1, 327 .flags = IORESOURCE_MEM, 328 }, { 329 .start = __PREG(Ser2HSCR0), 330 .end = __PREG(Ser2HSCR0) + 0x1c - 1, 331 .flags = IORESOURCE_MEM, 332 }, { 333 .start = __PREG(Ser2HSCR2), 334 .end = __PREG(Ser2HSCR2) + 0x04 - 1, 335 .flags = IORESOURCE_MEM, 336 }, { 337 .start = IRQ_Ser2ICP, 338 .end = IRQ_Ser2ICP, 339 .flags = IORESOURCE_IRQ, 340 } 341 }; 342 343 static struct platform_device sa11x0ir_device = { 344 .name = "sa11x0-ir", 345 .id = -1, 346 .num_resources = ARRAY_SIZE(sa11x0ir_resources), 347 .resource = sa11x0ir_resources, 348 }; 349 350 void sa11x0_register_irda(struct irda_platform_data *irda) 351 { 352 sa11x0_register_device(&sa11x0ir_device, irda); 353 } 354 355 static struct platform_device sa11x0rtc_device = { 356 .name = "sa1100-rtc", 357 .id = -1, 358 }; 359 360 static struct platform_device *sa11x0_devices[] __initdata = { 361 &sa11x0udc_device, 362 &sa11x0uart1_device, 363 &sa11x0uart3_device, 364 &sa11x0ssp_device, 365 &sa11x0pcmcia_device, 366 &sa11x0rtc_device, 367 }; 368 369 static int __init sa1100_init(void) 370 { 371 pm_power_off = sa1100_power_off; 372 return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices)); 373 } 374 375 arch_initcall(sa1100_init); 376 377 void (*sa1100fb_backlight_power)(int on); 378 void (*sa1100fb_lcd_power)(int on); 379 380 EXPORT_SYMBOL(sa1100fb_backlight_power); 381 EXPORT_SYMBOL(sa1100fb_lcd_power); 382 383 384 /* 385 * Common I/O mapping: 386 * 387 * Typically, static virtual address mappings are as follow: 388 * 389 * 0xf0000000-0xf3ffffff: miscellaneous stuff (CPLDs, etc.) 390 * 0xf4000000-0xf4ffffff: SA-1111 391 * 0xf5000000-0xf5ffffff: reserved (used by cache flushing area) 392 * 0xf6000000-0xfffeffff: reserved (internal SA1100 IO defined above) 393 * 0xffff0000-0xffff0fff: SA1100 exception vectors 394 * 0xffff2000-0xffff2fff: Minicache copy_user_page area 395 * 396 * Below 0xe8000000 is reserved for vm allocation. 397 * 398 * The machine specific code must provide the extra mapping beside the 399 * default mapping provided here. 400 */ 401 402 static struct map_desc standard_io_desc[] __initdata = { 403 { /* PCM */ 404 .virtual = 0xf8000000, 405 .pfn = __phys_to_pfn(0x80000000), 406 .length = 0x00100000, 407 .type = MT_DEVICE 408 }, { /* SCM */ 409 .virtual = 0xfa000000, 410 .pfn = __phys_to_pfn(0x90000000), 411 .length = 0x00100000, 412 .type = MT_DEVICE 413 }, { /* MER */ 414 .virtual = 0xfc000000, 415 .pfn = __phys_to_pfn(0xa0000000), 416 .length = 0x00100000, 417 .type = MT_DEVICE 418 }, { /* LCD + DMA */ 419 .virtual = 0xfe000000, 420 .pfn = __phys_to_pfn(0xb0000000), 421 .length = 0x00200000, 422 .type = MT_DEVICE 423 }, 424 }; 425 426 void __init sa1100_map_io(void) 427 { 428 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); 429 } 430 431 /* 432 * Disable the memory bus request/grant signals on the SA1110 to 433 * ensure that we don't receive spurious memory requests. We set 434 * the MBGNT signal false to ensure the SA1111 doesn't own the 435 * SDRAM bus. 436 */ 437 void __init sa1110_mb_disable(void) 438 { 439 unsigned long flags; 440 441 local_irq_save(flags); 442 443 PGSR &= ~GPIO_MBGNT; 444 GPCR = GPIO_MBGNT; 445 GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT; 446 447 GAFR &= ~(GPIO_MBGNT | GPIO_MBREQ); 448 449 local_irq_restore(flags); 450 } 451 452 /* 453 * If the system is going to use the SA-1111 DMA engines, set up 454 * the memory bus request/grant pins. 455 */ 456 void __devinit sa1110_mb_enable(void) 457 { 458 unsigned long flags; 459 460 local_irq_save(flags); 461 462 PGSR &= ~GPIO_MBGNT; 463 GPCR = GPIO_MBGNT; 464 GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT; 465 466 GAFR |= (GPIO_MBGNT | GPIO_MBREQ); 467 TUCR |= TUCR_MR; 468 469 local_irq_restore(flags); 470 } 471 472