1 /* 2 * linux/arch/arm/mach-sa1100/generic.c 3 * 4 * Author: Nicolas Pitre 5 * 6 * Code common to all SA11x0 machines. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 #include <linux/gpio.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/init.h> 16 #include <linux/delay.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/pm.h> 19 #include <linux/cpufreq.h> 20 #include <linux/ioport.h> 21 #include <linux/platform_device.h> 22 #include <linux/reboot.h> 23 24 #include <video/sa1100fb.h> 25 26 #include <soc/sa1100/pwer.h> 27 28 #include <asm/div64.h> 29 #include <asm/mach/map.h> 30 #include <asm/mach/flash.h> 31 #include <asm/irq.h> 32 #include <asm/system_misc.h> 33 34 #include <mach/hardware.h> 35 #include <mach/irqs.h> 36 37 #include "generic.h" 38 #include <clocksource/pxa.h> 39 40 unsigned int reset_status; 41 EXPORT_SYMBOL(reset_status); 42 43 #define NR_FREQS 16 44 45 /* 46 * This table is setup for a 3.6864MHz Crystal. 47 */ 48 struct cpufreq_frequency_table sa11x0_freq_table[NR_FREQS+1] = { 49 { .frequency = 59000, /* 59.0 MHz */}, 50 { .frequency = 73700, /* 73.7 MHz */}, 51 { .frequency = 88500, /* 88.5 MHz */}, 52 { .frequency = 103200, /* 103.2 MHz */}, 53 { .frequency = 118000, /* 118.0 MHz */}, 54 { .frequency = 132700, /* 132.7 MHz */}, 55 { .frequency = 147500, /* 147.5 MHz */}, 56 { .frequency = 162200, /* 162.2 MHz */}, 57 { .frequency = 176900, /* 176.9 MHz */}, 58 { .frequency = 191700, /* 191.7 MHz */}, 59 { .frequency = 206400, /* 206.4 MHz */}, 60 { .frequency = 221200, /* 221.2 MHz */}, 61 { .frequency = 235900, /* 235.9 MHz */}, 62 { .frequency = 250700, /* 250.7 MHz */}, 63 { .frequency = 265400, /* 265.4 MHz */}, 64 { .frequency = 280200, /* 280.2 MHz */}, 65 { .frequency = CPUFREQ_TABLE_END, }, 66 }; 67 68 unsigned int sa11x0_getspeed(unsigned int cpu) 69 { 70 if (cpu) 71 return 0; 72 return sa11x0_freq_table[PPCR & 0xf].frequency; 73 } 74 75 /* 76 * Default power-off for SA1100 77 */ 78 static void sa1100_power_off(void) 79 { 80 mdelay(100); 81 local_irq_disable(); 82 /* disable internal oscillator, float CS lines */ 83 PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS); 84 /* enable wake-up on GPIO0 (Assabet...) */ 85 PWER = GFER = GRER = 1; 86 /* 87 * set scratchpad to zero, just in case it is used as a 88 * restart address by the bootloader. 89 */ 90 PSPR = 0; 91 /* enter sleep mode */ 92 PMCR = PMCR_SF; 93 } 94 95 void sa11x0_restart(enum reboot_mode mode, const char *cmd) 96 { 97 if (mode == REBOOT_SOFT) { 98 /* Jump into ROM at address 0 */ 99 soft_restart(0); 100 } else { 101 /* Use on-chip reset capability */ 102 RSRR = RSRR_SWR; 103 } 104 } 105 106 static void sa11x0_register_device(struct platform_device *dev, void *data) 107 { 108 int err; 109 dev->dev.platform_data = data; 110 err = platform_device_register(dev); 111 if (err) 112 printk(KERN_ERR "Unable to register device %s: %d\n", 113 dev->name, err); 114 } 115 116 117 static struct resource sa11x0udc_resources[] = { 118 [0] = DEFINE_RES_MEM(__PREG(Ser0UDCCR), SZ_64K), 119 [1] = DEFINE_RES_IRQ(IRQ_Ser0UDC), 120 }; 121 122 static u64 sa11x0udc_dma_mask = 0xffffffffUL; 123 124 static struct platform_device sa11x0udc_device = { 125 .name = "sa11x0-udc", 126 .id = -1, 127 .dev = { 128 .dma_mask = &sa11x0udc_dma_mask, 129 .coherent_dma_mask = 0xffffffff, 130 }, 131 .num_resources = ARRAY_SIZE(sa11x0udc_resources), 132 .resource = sa11x0udc_resources, 133 }; 134 135 static struct resource sa11x0uart1_resources[] = { 136 [0] = DEFINE_RES_MEM(__PREG(Ser1UTCR0), SZ_64K), 137 [1] = DEFINE_RES_IRQ(IRQ_Ser1UART), 138 }; 139 140 static struct platform_device sa11x0uart1_device = { 141 .name = "sa11x0-uart", 142 .id = 1, 143 .num_resources = ARRAY_SIZE(sa11x0uart1_resources), 144 .resource = sa11x0uart1_resources, 145 }; 146 147 static struct resource sa11x0uart3_resources[] = { 148 [0] = DEFINE_RES_MEM(__PREG(Ser3UTCR0), SZ_64K), 149 [1] = DEFINE_RES_IRQ(IRQ_Ser3UART), 150 }; 151 152 static struct platform_device sa11x0uart3_device = { 153 .name = "sa11x0-uart", 154 .id = 3, 155 .num_resources = ARRAY_SIZE(sa11x0uart3_resources), 156 .resource = sa11x0uart3_resources, 157 }; 158 159 static struct resource sa11x0mcp_resources[] = { 160 [0] = DEFINE_RES_MEM(__PREG(Ser4MCCR0), SZ_64K), 161 [1] = DEFINE_RES_MEM(__PREG(Ser4MCCR1), 4), 162 [2] = DEFINE_RES_IRQ(IRQ_Ser4MCP), 163 }; 164 165 static u64 sa11x0mcp_dma_mask = 0xffffffffUL; 166 167 static struct platform_device sa11x0mcp_device = { 168 .name = "sa11x0-mcp", 169 .id = -1, 170 .dev = { 171 .dma_mask = &sa11x0mcp_dma_mask, 172 .coherent_dma_mask = 0xffffffff, 173 }, 174 .num_resources = ARRAY_SIZE(sa11x0mcp_resources), 175 .resource = sa11x0mcp_resources, 176 }; 177 178 void __init sa11x0_ppc_configure_mcp(void) 179 { 180 /* Setup the PPC unit for the MCP */ 181 PPDR &= ~PPC_RXD4; 182 PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM; 183 PSDR |= PPC_RXD4; 184 PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); 185 PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); 186 } 187 188 void sa11x0_register_mcp(struct mcp_plat_data *data) 189 { 190 sa11x0_register_device(&sa11x0mcp_device, data); 191 } 192 193 static struct resource sa11x0ssp_resources[] = { 194 [0] = DEFINE_RES_MEM(0x80070000, SZ_64K), 195 [1] = DEFINE_RES_IRQ(IRQ_Ser4SSP), 196 }; 197 198 static u64 sa11x0ssp_dma_mask = 0xffffffffUL; 199 200 static struct platform_device sa11x0ssp_device = { 201 .name = "sa11x0-ssp", 202 .id = -1, 203 .dev = { 204 .dma_mask = &sa11x0ssp_dma_mask, 205 .coherent_dma_mask = 0xffffffff, 206 }, 207 .num_resources = ARRAY_SIZE(sa11x0ssp_resources), 208 .resource = sa11x0ssp_resources, 209 }; 210 211 static struct resource sa11x0fb_resources[] = { 212 [0] = DEFINE_RES_MEM(0xb0100000, SZ_64K), 213 [1] = DEFINE_RES_IRQ(IRQ_LCD), 214 }; 215 216 static struct platform_device sa11x0fb_device = { 217 .name = "sa11x0-fb", 218 .id = -1, 219 .dev = { 220 .coherent_dma_mask = 0xffffffff, 221 }, 222 .num_resources = ARRAY_SIZE(sa11x0fb_resources), 223 .resource = sa11x0fb_resources, 224 }; 225 226 void sa11x0_register_lcd(struct sa1100fb_mach_info *inf) 227 { 228 sa11x0_register_device(&sa11x0fb_device, inf); 229 } 230 231 static struct platform_device sa11x0pcmcia_device = { 232 .name = "sa11x0-pcmcia", 233 .id = -1, 234 }; 235 236 static struct platform_device sa11x0mtd_device = { 237 .name = "sa1100-mtd", 238 .id = -1, 239 }; 240 241 void sa11x0_register_mtd(struct flash_platform_data *flash, 242 struct resource *res, int nr) 243 { 244 flash->name = "sa1100"; 245 sa11x0mtd_device.resource = res; 246 sa11x0mtd_device.num_resources = nr; 247 sa11x0_register_device(&sa11x0mtd_device, flash); 248 } 249 250 static struct resource sa11x0ir_resources[] = { 251 DEFINE_RES_MEM(__PREG(Ser2UTCR0), 0x24), 252 DEFINE_RES_MEM(__PREG(Ser2HSCR0), 0x1c), 253 DEFINE_RES_MEM(__PREG(Ser2HSCR2), 0x04), 254 DEFINE_RES_IRQ(IRQ_Ser2ICP), 255 }; 256 257 static struct platform_device sa11x0ir_device = { 258 .name = "sa11x0-ir", 259 .id = -1, 260 .num_resources = ARRAY_SIZE(sa11x0ir_resources), 261 .resource = sa11x0ir_resources, 262 }; 263 264 void sa11x0_register_irda(struct irda_platform_data *irda) 265 { 266 sa11x0_register_device(&sa11x0ir_device, irda); 267 } 268 269 static struct resource sa1100_rtc_resources[] = { 270 DEFINE_RES_MEM(0x90010000, 0x40), 271 DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"), 272 DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"), 273 }; 274 275 static struct platform_device sa11x0rtc_device = { 276 .name = "sa1100-rtc", 277 .id = -1, 278 .num_resources = ARRAY_SIZE(sa1100_rtc_resources), 279 .resource = sa1100_rtc_resources, 280 }; 281 282 static struct resource sa11x0dma_resources[] = { 283 DEFINE_RES_MEM(DMA_PHYS, DMA_SIZE), 284 DEFINE_RES_IRQ(IRQ_DMA0), 285 DEFINE_RES_IRQ(IRQ_DMA1), 286 DEFINE_RES_IRQ(IRQ_DMA2), 287 DEFINE_RES_IRQ(IRQ_DMA3), 288 DEFINE_RES_IRQ(IRQ_DMA4), 289 DEFINE_RES_IRQ(IRQ_DMA5), 290 }; 291 292 static u64 sa11x0dma_dma_mask = DMA_BIT_MASK(32); 293 294 static struct platform_device sa11x0dma_device = { 295 .name = "sa11x0-dma", 296 .id = -1, 297 .dev = { 298 .dma_mask = &sa11x0dma_dma_mask, 299 .coherent_dma_mask = 0xffffffff, 300 }, 301 .num_resources = ARRAY_SIZE(sa11x0dma_resources), 302 .resource = sa11x0dma_resources, 303 }; 304 305 static struct platform_device *sa11x0_devices[] __initdata = { 306 &sa11x0udc_device, 307 &sa11x0uart1_device, 308 &sa11x0uart3_device, 309 &sa11x0ssp_device, 310 &sa11x0pcmcia_device, 311 &sa11x0rtc_device, 312 &sa11x0dma_device, 313 }; 314 315 static int __init sa1100_init(void) 316 { 317 pm_power_off = sa1100_power_off; 318 return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices)); 319 } 320 321 arch_initcall(sa1100_init); 322 323 void __init sa11x0_init_late(void) 324 { 325 sa11x0_pm_init(); 326 } 327 328 /* 329 * Common I/O mapping: 330 * 331 * Typically, static virtual address mappings are as follow: 332 * 333 * 0xf0000000-0xf3ffffff: miscellaneous stuff (CPLDs, etc.) 334 * 0xf4000000-0xf4ffffff: SA-1111 335 * 0xf5000000-0xf5ffffff: reserved (used by cache flushing area) 336 * 0xf6000000-0xfffeffff: reserved (internal SA1100 IO defined above) 337 * 0xffff0000-0xffff0fff: SA1100 exception vectors 338 * 0xffff2000-0xffff2fff: Minicache copy_user_page area 339 * 340 * Below 0xe8000000 is reserved for vm allocation. 341 * 342 * The machine specific code must provide the extra mapping beside the 343 * default mapping provided here. 344 */ 345 346 static struct map_desc standard_io_desc[] __initdata = { 347 { /* PCM */ 348 .virtual = 0xf8000000, 349 .pfn = __phys_to_pfn(0x80000000), 350 .length = 0x00100000, 351 .type = MT_DEVICE 352 }, { /* SCM */ 353 .virtual = 0xfa000000, 354 .pfn = __phys_to_pfn(0x90000000), 355 .length = 0x00100000, 356 .type = MT_DEVICE 357 }, { /* MER */ 358 .virtual = 0xfc000000, 359 .pfn = __phys_to_pfn(0xa0000000), 360 .length = 0x00100000, 361 .type = MT_DEVICE 362 }, { /* LCD + DMA */ 363 .virtual = 0xfe000000, 364 .pfn = __phys_to_pfn(0xb0000000), 365 .length = 0x00200000, 366 .type = MT_DEVICE 367 }, 368 }; 369 370 void __init sa1100_map_io(void) 371 { 372 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); 373 } 374 375 void __init sa1100_timer_init(void) 376 { 377 pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x90000000), 3686400); 378 } 379 380 /* 381 * Disable the memory bus request/grant signals on the SA1110 to 382 * ensure that we don't receive spurious memory requests. We set 383 * the MBGNT signal false to ensure the SA1111 doesn't own the 384 * SDRAM bus. 385 */ 386 void sa1110_mb_disable(void) 387 { 388 unsigned long flags; 389 390 local_irq_save(flags); 391 392 PGSR &= ~GPIO_MBGNT; 393 GPCR = GPIO_MBGNT; 394 GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT; 395 396 GAFR &= ~(GPIO_MBGNT | GPIO_MBREQ); 397 398 local_irq_restore(flags); 399 } 400 401 /* 402 * If the system is going to use the SA-1111 DMA engines, set up 403 * the memory bus request/grant pins. 404 */ 405 void sa1110_mb_enable(void) 406 { 407 unsigned long flags; 408 409 local_irq_save(flags); 410 411 PGSR &= ~GPIO_MBGNT; 412 GPCR = GPIO_MBGNT; 413 GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT; 414 415 GAFR |= (GPIO_MBGNT | GPIO_MBREQ); 416 TUCR |= TUCR_MR; 417 418 local_irq_restore(flags); 419 } 420 421 int sa11x0_gpio_set_wake(unsigned int gpio, unsigned int on) 422 { 423 if (on) 424 PWER |= BIT(gpio); 425 else 426 PWER &= ~BIT(gpio); 427 428 return 0; 429 } 430 431 int sa11x0_sc_set_wake(unsigned int irq, unsigned int on) 432 { 433 if (BIT(irq) != IC_RTCAlrm) 434 return -EINVAL; 435 436 if (on) 437 PWER |= PWER_RTC; 438 else 439 PWER &= ~PWER_RTC; 440 441 return 0; 442 } 443