1 /* 2 * linux/arch/arm/mach-sa1100/generic.c 3 * 4 * Author: Nicolas Pitre 5 * 6 * Code common to all SA11x0 machines. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 #include <linux/module.h> 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/cpufreq.h> 18 #include <linux/ioport.h> 19 #include <linux/sched.h> /* just for sched_clock() - funny that */ 20 #include <linux/platform_device.h> 21 22 #include <asm/div64.h> 23 #include <asm/cnt32_to_63.h> 24 #include <asm/hardware.h> 25 #include <asm/system.h> 26 #include <asm/pgtable.h> 27 #include <asm/mach/map.h> 28 #include <asm/mach/flash.h> 29 #include <asm/irq.h> 30 #include <asm/gpio.h> 31 32 #include "generic.h" 33 34 #define NR_FREQS 16 35 36 /* 37 * This table is setup for a 3.6864MHz Crystal. 38 */ 39 static const unsigned short cclk_frequency_100khz[NR_FREQS] = { 40 590, /* 59.0 MHz */ 41 737, /* 73.7 MHz */ 42 885, /* 88.5 MHz */ 43 1032, /* 103.2 MHz */ 44 1180, /* 118.0 MHz */ 45 1327, /* 132.7 MHz */ 46 1475, /* 147.5 MHz */ 47 1622, /* 162.2 MHz */ 48 1769, /* 176.9 MHz */ 49 1917, /* 191.7 MHz */ 50 2064, /* 206.4 MHz */ 51 2212, /* 221.2 MHz */ 52 2359, /* 235.9 MHz */ 53 2507, /* 250.7 MHz */ 54 2654, /* 265.4 MHz */ 55 2802 /* 280.2 MHz */ 56 }; 57 58 #if defined(CONFIG_CPU_FREQ_SA1100) || defined(CONFIG_CPU_FREQ_SA1110) 59 /* rounds up(!) */ 60 unsigned int sa11x0_freq_to_ppcr(unsigned int khz) 61 { 62 int i; 63 64 khz /= 100; 65 66 for (i = 0; i < NR_FREQS; i++) 67 if (cclk_frequency_100khz[i] >= khz) 68 break; 69 70 return i; 71 } 72 73 unsigned int sa11x0_ppcr_to_freq(unsigned int idx) 74 { 75 unsigned int freq = 0; 76 if (idx < NR_FREQS) 77 freq = cclk_frequency_100khz[idx] * 100; 78 return freq; 79 } 80 81 82 /* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on 83 * this platform, anyway. 84 */ 85 int sa11x0_verify_speed(struct cpufreq_policy *policy) 86 { 87 unsigned int tmp; 88 if (policy->cpu) 89 return -EINVAL; 90 91 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq); 92 93 /* make sure that at least one frequency is within the policy */ 94 tmp = cclk_frequency_100khz[sa11x0_freq_to_ppcr(policy->min)] * 100; 95 if (tmp > policy->max) 96 policy->max = tmp; 97 98 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq); 99 100 return 0; 101 } 102 103 unsigned int sa11x0_getspeed(unsigned int cpu) 104 { 105 if (cpu) 106 return 0; 107 return cclk_frequency_100khz[PPCR & 0xf] * 100; 108 } 109 110 #else 111 /* 112 * We still need to provide this so building without cpufreq works. 113 */ 114 unsigned int cpufreq_get(unsigned int cpu) 115 { 116 return cclk_frequency_100khz[PPCR & 0xf] * 100; 117 } 118 EXPORT_SYMBOL(cpufreq_get); 119 #endif 120 121 /* 122 * This is the SA11x0 sched_clock implementation. This has 123 * a resolution of 271ns, and a maximum value of 32025597s (370 days). 124 * 125 * The return value is guaranteed to be monotonic in that range as 126 * long as there is always less than 582 seconds between successive 127 * calls to this function. 128 * 129 * ( * 1E9 / 3686400 => * 78125 / 288) 130 */ 131 unsigned long long sched_clock(void) 132 { 133 unsigned long long v = cnt32_to_63(OSCR); 134 135 /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */ 136 v *= 78125<<1; 137 do_div(v, 288<<1); 138 139 return v; 140 } 141 142 int gpio_direction_input(unsigned gpio) 143 { 144 unsigned long flags; 145 146 if (gpio > GPIO_MAX) 147 return -EINVAL; 148 149 local_irq_save(flags); 150 GPDR &= ~GPIO_GPIO(gpio); 151 local_irq_restore(flags); 152 return 0; 153 } 154 155 EXPORT_SYMBOL(gpio_direction_input); 156 157 int gpio_direction_output(unsigned gpio, int value) 158 { 159 unsigned long flags; 160 161 if (gpio > GPIO_MAX) 162 return -EINVAL; 163 164 local_irq_save(flags); 165 gpio_set_value(gpio, value); 166 GPDR |= GPIO_GPIO(gpio); 167 local_irq_restore(flags); 168 return 0; 169 } 170 171 EXPORT_SYMBOL(gpio_direction_output); 172 173 /* 174 * Default power-off for SA1100 175 */ 176 static void sa1100_power_off(void) 177 { 178 mdelay(100); 179 local_irq_disable(); 180 /* disable internal oscillator, float CS lines */ 181 PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS); 182 /* enable wake-up on GPIO0 (Assabet...) */ 183 PWER = GFER = GRER = 1; 184 /* 185 * set scratchpad to zero, just in case it is used as a 186 * restart address by the bootloader. 187 */ 188 PSPR = 0; 189 /* enter sleep mode */ 190 PMCR = PMCR_SF; 191 } 192 193 static struct resource sa11x0udc_resources[] = { 194 [0] = { 195 .start = 0x80000000, 196 .end = 0x8000ffff, 197 .flags = IORESOURCE_MEM, 198 }, 199 }; 200 201 static u64 sa11x0udc_dma_mask = 0xffffffffUL; 202 203 static struct platform_device sa11x0udc_device = { 204 .name = "sa11x0-udc", 205 .id = -1, 206 .dev = { 207 .dma_mask = &sa11x0udc_dma_mask, 208 .coherent_dma_mask = 0xffffffff, 209 }, 210 .num_resources = ARRAY_SIZE(sa11x0udc_resources), 211 .resource = sa11x0udc_resources, 212 }; 213 214 static struct resource sa11x0uart1_resources[] = { 215 [0] = { 216 .start = 0x80010000, 217 .end = 0x8001ffff, 218 .flags = IORESOURCE_MEM, 219 }, 220 }; 221 222 static struct platform_device sa11x0uart1_device = { 223 .name = "sa11x0-uart", 224 .id = 1, 225 .num_resources = ARRAY_SIZE(sa11x0uart1_resources), 226 .resource = sa11x0uart1_resources, 227 }; 228 229 static struct resource sa11x0uart3_resources[] = { 230 [0] = { 231 .start = 0x80050000, 232 .end = 0x8005ffff, 233 .flags = IORESOURCE_MEM, 234 }, 235 }; 236 237 static struct platform_device sa11x0uart3_device = { 238 .name = "sa11x0-uart", 239 .id = 3, 240 .num_resources = ARRAY_SIZE(sa11x0uart3_resources), 241 .resource = sa11x0uart3_resources, 242 }; 243 244 static struct resource sa11x0mcp_resources[] = { 245 [0] = { 246 .start = 0x80060000, 247 .end = 0x8006ffff, 248 .flags = IORESOURCE_MEM, 249 }, 250 }; 251 252 static u64 sa11x0mcp_dma_mask = 0xffffffffUL; 253 254 static struct platform_device sa11x0mcp_device = { 255 .name = "sa11x0-mcp", 256 .id = -1, 257 .dev = { 258 .dma_mask = &sa11x0mcp_dma_mask, 259 .coherent_dma_mask = 0xffffffff, 260 }, 261 .num_resources = ARRAY_SIZE(sa11x0mcp_resources), 262 .resource = sa11x0mcp_resources, 263 }; 264 265 void sa11x0_set_mcp_data(struct mcp_plat_data *data) 266 { 267 sa11x0mcp_device.dev.platform_data = data; 268 } 269 270 static struct resource sa11x0ssp_resources[] = { 271 [0] = { 272 .start = 0x80070000, 273 .end = 0x8007ffff, 274 .flags = IORESOURCE_MEM, 275 }, 276 }; 277 278 static u64 sa11x0ssp_dma_mask = 0xffffffffUL; 279 280 static struct platform_device sa11x0ssp_device = { 281 .name = "sa11x0-ssp", 282 .id = -1, 283 .dev = { 284 .dma_mask = &sa11x0ssp_dma_mask, 285 .coherent_dma_mask = 0xffffffff, 286 }, 287 .num_resources = ARRAY_SIZE(sa11x0ssp_resources), 288 .resource = sa11x0ssp_resources, 289 }; 290 291 static struct resource sa11x0fb_resources[] = { 292 [0] = { 293 .start = 0xb0100000, 294 .end = 0xb010ffff, 295 .flags = IORESOURCE_MEM, 296 }, 297 [1] = { 298 .start = IRQ_LCD, 299 .end = IRQ_LCD, 300 .flags = IORESOURCE_IRQ, 301 }, 302 }; 303 304 static struct platform_device sa11x0fb_device = { 305 .name = "sa11x0-fb", 306 .id = -1, 307 .dev = { 308 .coherent_dma_mask = 0xffffffff, 309 }, 310 .num_resources = ARRAY_SIZE(sa11x0fb_resources), 311 .resource = sa11x0fb_resources, 312 }; 313 314 static struct platform_device sa11x0pcmcia_device = { 315 .name = "sa11x0-pcmcia", 316 .id = -1, 317 }; 318 319 static struct platform_device sa11x0mtd_device = { 320 .name = "flash", 321 .id = -1, 322 }; 323 324 void sa11x0_set_flash_data(struct flash_platform_data *flash, 325 struct resource *res, int nr) 326 { 327 flash->name = "sa1100"; 328 sa11x0mtd_device.dev.platform_data = flash; 329 sa11x0mtd_device.resource = res; 330 sa11x0mtd_device.num_resources = nr; 331 } 332 333 static struct resource sa11x0ir_resources[] = { 334 { 335 .start = __PREG(Ser2UTCR0), 336 .end = __PREG(Ser2UTCR0) + 0x24 - 1, 337 .flags = IORESOURCE_MEM, 338 }, { 339 .start = __PREG(Ser2HSCR0), 340 .end = __PREG(Ser2HSCR0) + 0x1c - 1, 341 .flags = IORESOURCE_MEM, 342 }, { 343 .start = __PREG(Ser2HSCR2), 344 .end = __PREG(Ser2HSCR2) + 0x04 - 1, 345 .flags = IORESOURCE_MEM, 346 }, { 347 .start = IRQ_Ser2ICP, 348 .end = IRQ_Ser2ICP, 349 .flags = IORESOURCE_IRQ, 350 } 351 }; 352 353 static struct platform_device sa11x0ir_device = { 354 .name = "sa11x0-ir", 355 .id = -1, 356 .num_resources = ARRAY_SIZE(sa11x0ir_resources), 357 .resource = sa11x0ir_resources, 358 }; 359 360 void sa11x0_set_irda_data(struct irda_platform_data *irda) 361 { 362 sa11x0ir_device.dev.platform_data = irda; 363 } 364 365 static struct platform_device sa11x0rtc_device = { 366 .name = "sa1100-rtc", 367 .id = -1, 368 }; 369 370 static struct platform_device *sa11x0_devices[] __initdata = { 371 &sa11x0udc_device, 372 &sa11x0uart1_device, 373 &sa11x0uart3_device, 374 &sa11x0mcp_device, 375 &sa11x0ssp_device, 376 &sa11x0pcmcia_device, 377 &sa11x0fb_device, 378 &sa11x0mtd_device, 379 &sa11x0rtc_device, 380 }; 381 382 static int __init sa1100_init(void) 383 { 384 pm_power_off = sa1100_power_off; 385 386 if (sa11x0ir_device.dev.platform_data) 387 platform_device_register(&sa11x0ir_device); 388 389 return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices)); 390 } 391 392 arch_initcall(sa1100_init); 393 394 void (*sa1100fb_backlight_power)(int on); 395 void (*sa1100fb_lcd_power)(int on); 396 397 EXPORT_SYMBOL(sa1100fb_backlight_power); 398 EXPORT_SYMBOL(sa1100fb_lcd_power); 399 400 401 /* 402 * Common I/O mapping: 403 * 404 * Typically, static virtual address mappings are as follow: 405 * 406 * 0xf0000000-0xf3ffffff: miscellaneous stuff (CPLDs, etc.) 407 * 0xf4000000-0xf4ffffff: SA-1111 408 * 0xf5000000-0xf5ffffff: reserved (used by cache flushing area) 409 * 0xf6000000-0xfffeffff: reserved (internal SA1100 IO defined above) 410 * 0xffff0000-0xffff0fff: SA1100 exception vectors 411 * 0xffff2000-0xffff2fff: Minicache copy_user_page area 412 * 413 * Below 0xe8000000 is reserved for vm allocation. 414 * 415 * The machine specific code must provide the extra mapping beside the 416 * default mapping provided here. 417 */ 418 419 static struct map_desc standard_io_desc[] __initdata = { 420 { /* PCM */ 421 .virtual = 0xf8000000, 422 .pfn = __phys_to_pfn(0x80000000), 423 .length = 0x00100000, 424 .type = MT_DEVICE 425 }, { /* SCM */ 426 .virtual = 0xfa000000, 427 .pfn = __phys_to_pfn(0x90000000), 428 .length = 0x00100000, 429 .type = MT_DEVICE 430 }, { /* MER */ 431 .virtual = 0xfc000000, 432 .pfn = __phys_to_pfn(0xa0000000), 433 .length = 0x00100000, 434 .type = MT_DEVICE 435 }, { /* LCD + DMA */ 436 .virtual = 0xfe000000, 437 .pfn = __phys_to_pfn(0xb0000000), 438 .length = 0x00200000, 439 .type = MT_DEVICE 440 }, 441 }; 442 443 void __init sa1100_map_io(void) 444 { 445 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); 446 } 447 448 /* 449 * Disable the memory bus request/grant signals on the SA1110 to 450 * ensure that we don't receive spurious memory requests. We set 451 * the MBGNT signal false to ensure the SA1111 doesn't own the 452 * SDRAM bus. 453 */ 454 void __init sa1110_mb_disable(void) 455 { 456 unsigned long flags; 457 458 local_irq_save(flags); 459 460 PGSR &= ~GPIO_MBGNT; 461 GPCR = GPIO_MBGNT; 462 GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT; 463 464 GAFR &= ~(GPIO_MBGNT | GPIO_MBREQ); 465 466 local_irq_restore(flags); 467 } 468 469 /* 470 * If the system is going to use the SA-1111 DMA engines, set up 471 * the memory bus request/grant pins. 472 */ 473 void __init sa1110_mb_enable(void) 474 { 475 unsigned long flags; 476 477 local_irq_save(flags); 478 479 PGSR &= ~GPIO_MBGNT; 480 GPCR = GPIO_MBGNT; 481 GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT; 482 483 GAFR |= (GPIO_MBGNT | GPIO_MBREQ); 484 TUCR |= TUCR_MR; 485 486 local_irq_restore(flags); 487 } 488 489