1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * linux/arch/arm/mach-sa1100/clock.c 4 */ 5 #include <linux/module.h> 6 #include <linux/kernel.h> 7 #include <linux/device.h> 8 #include <linux/list.h> 9 #include <linux/errno.h> 10 #include <linux/err.h> 11 #include <linux/string.h> 12 #include <linux/clk.h> 13 #include <linux/spinlock.h> 14 #include <linux/mutex.h> 15 #include <linux/io.h> 16 #include <linux/clkdev.h> 17 18 #include <mach/hardware.h> 19 #include <mach/generic.h> 20 21 struct clkops { 22 void (*enable)(struct clk *); 23 void (*disable)(struct clk *); 24 unsigned long (*get_rate)(struct clk *); 25 }; 26 27 struct clk { 28 const struct clkops *ops; 29 unsigned int enabled; 30 }; 31 32 #define DEFINE_CLK(_name, _ops) \ 33 struct clk clk_##_name = { \ 34 .ops = _ops, \ 35 } 36 37 static DEFINE_SPINLOCK(clocks_lock); 38 39 /* Dummy clk routine to build generic kernel parts that may be using them */ 40 long clk_round_rate(struct clk *clk, unsigned long rate) 41 { 42 return clk_get_rate(clk); 43 } 44 EXPORT_SYMBOL(clk_round_rate); 45 46 int clk_set_rate(struct clk *clk, unsigned long rate) 47 { 48 return 0; 49 } 50 EXPORT_SYMBOL(clk_set_rate); 51 52 int clk_set_parent(struct clk *clk, struct clk *parent) 53 { 54 return 0; 55 } 56 EXPORT_SYMBOL(clk_set_parent); 57 58 struct clk *clk_get_parent(struct clk *clk) 59 { 60 return NULL; 61 } 62 EXPORT_SYMBOL(clk_get_parent); 63 64 static void clk_gpio27_enable(struct clk *clk) 65 { 66 /* 67 * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111: 68 * (SA-1110 Developer's Manual, section 9.1.2.1) 69 */ 70 GAFR |= GPIO_32_768kHz; 71 GPDR |= GPIO_32_768kHz; 72 TUCR = TUCR_3_6864MHz; 73 } 74 75 static void clk_gpio27_disable(struct clk *clk) 76 { 77 TUCR = 0; 78 GPDR &= ~GPIO_32_768kHz; 79 GAFR &= ~GPIO_32_768kHz; 80 } 81 82 static void clk_cpu_enable(struct clk *clk) 83 { 84 } 85 86 static void clk_cpu_disable(struct clk *clk) 87 { 88 } 89 90 static unsigned long clk_cpu_get_rate(struct clk *clk) 91 { 92 return sa11x0_getspeed(0) * 1000; 93 } 94 95 int clk_enable(struct clk *clk) 96 { 97 unsigned long flags; 98 99 if (clk) { 100 spin_lock_irqsave(&clocks_lock, flags); 101 if (clk->enabled++ == 0) 102 clk->ops->enable(clk); 103 spin_unlock_irqrestore(&clocks_lock, flags); 104 } 105 106 return 0; 107 } 108 EXPORT_SYMBOL(clk_enable); 109 110 void clk_disable(struct clk *clk) 111 { 112 unsigned long flags; 113 114 if (clk) { 115 WARN_ON(clk->enabled == 0); 116 spin_lock_irqsave(&clocks_lock, flags); 117 if (--clk->enabled == 0) 118 clk->ops->disable(clk); 119 spin_unlock_irqrestore(&clocks_lock, flags); 120 } 121 } 122 EXPORT_SYMBOL(clk_disable); 123 124 unsigned long clk_get_rate(struct clk *clk) 125 { 126 if (clk && clk->ops && clk->ops->get_rate) 127 return clk->ops->get_rate(clk); 128 129 return 0; 130 } 131 EXPORT_SYMBOL(clk_get_rate); 132 133 const struct clkops clk_gpio27_ops = { 134 .enable = clk_gpio27_enable, 135 .disable = clk_gpio27_disable, 136 }; 137 138 const struct clkops clk_cpu_ops = { 139 .enable = clk_cpu_enable, 140 .disable = clk_cpu_disable, 141 .get_rate = clk_cpu_get_rate, 142 }; 143 144 static DEFINE_CLK(gpio27, &clk_gpio27_ops); 145 146 static DEFINE_CLK(cpu, &clk_cpu_ops); 147 148 static unsigned long clk_36864_get_rate(struct clk *clk) 149 { 150 return 3686400; 151 } 152 153 static struct clkops clk_36864_ops = { 154 .enable = clk_cpu_enable, 155 .disable = clk_cpu_disable, 156 .get_rate = clk_36864_get_rate, 157 }; 158 159 static DEFINE_CLK(36864, &clk_36864_ops); 160 161 static struct clk_lookup sa11xx_clkregs[] = { 162 CLKDEV_INIT("sa1111.0", NULL, &clk_gpio27), 163 CLKDEV_INIT("sa1100-rtc", NULL, NULL), 164 CLKDEV_INIT("sa11x0-fb", NULL, &clk_cpu), 165 CLKDEV_INIT("sa11x0-pcmcia", NULL, &clk_cpu), 166 CLKDEV_INIT("sa11x0-pcmcia.0", NULL, &clk_cpu), 167 CLKDEV_INIT("sa11x0-pcmcia.1", NULL, &clk_cpu), 168 /* sa1111 names devices using internal offsets, PCMCIA is at 0x1800 */ 169 CLKDEV_INIT("1800", NULL, &clk_cpu), 170 CLKDEV_INIT(NULL, "OSTIMER0", &clk_36864), 171 }; 172 173 int __init sa11xx_clk_init(void) 174 { 175 clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs)); 176 return 0; 177 } 178