1 /* 2 * linux/arch/arm/mach-sa1100/clock.c 3 */ 4 #include <linux/module.h> 5 #include <linux/kernel.h> 6 #include <linux/device.h> 7 #include <linux/list.h> 8 #include <linux/errno.h> 9 #include <linux/err.h> 10 #include <linux/string.h> 11 #include <linux/clk.h> 12 #include <linux/spinlock.h> 13 #include <linux/mutex.h> 14 #include <linux/io.h> 15 #include <linux/clkdev.h> 16 17 #include <mach/hardware.h> 18 #include <mach/generic.h> 19 20 struct clkops { 21 void (*enable)(struct clk *); 22 void (*disable)(struct clk *); 23 unsigned long (*get_rate)(struct clk *); 24 }; 25 26 struct clk { 27 const struct clkops *ops; 28 unsigned int enabled; 29 }; 30 31 #define DEFINE_CLK(_name, _ops) \ 32 struct clk clk_##_name = { \ 33 .ops = _ops, \ 34 } 35 36 static DEFINE_SPINLOCK(clocks_lock); 37 38 /* Dummy clk routine to build generic kernel parts that may be using them */ 39 long clk_round_rate(struct clk *clk, unsigned long rate) 40 { 41 return clk_get_rate(clk); 42 } 43 EXPORT_SYMBOL(clk_round_rate); 44 45 int clk_set_rate(struct clk *clk, unsigned long rate) 46 { 47 return 0; 48 } 49 EXPORT_SYMBOL(clk_set_rate); 50 51 int clk_set_parent(struct clk *clk, struct clk *parent) 52 { 53 return 0; 54 } 55 EXPORT_SYMBOL(clk_set_parent); 56 57 struct clk *clk_get_parent(struct clk *clk) 58 { 59 return NULL; 60 } 61 EXPORT_SYMBOL(clk_get_parent); 62 63 static void clk_gpio27_enable(struct clk *clk) 64 { 65 /* 66 * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111: 67 * (SA-1110 Developer's Manual, section 9.1.2.1) 68 */ 69 GAFR |= GPIO_32_768kHz; 70 GPDR |= GPIO_32_768kHz; 71 TUCR = TUCR_3_6864MHz; 72 } 73 74 static void clk_gpio27_disable(struct clk *clk) 75 { 76 TUCR = 0; 77 GPDR &= ~GPIO_32_768kHz; 78 GAFR &= ~GPIO_32_768kHz; 79 } 80 81 static void clk_cpu_enable(struct clk *clk) 82 { 83 } 84 85 static void clk_cpu_disable(struct clk *clk) 86 { 87 } 88 89 static unsigned long clk_cpu_get_rate(struct clk *clk) 90 { 91 return sa11x0_getspeed(0) * 1000; 92 } 93 94 int clk_enable(struct clk *clk) 95 { 96 unsigned long flags; 97 98 if (clk) { 99 spin_lock_irqsave(&clocks_lock, flags); 100 if (clk->enabled++ == 0) 101 clk->ops->enable(clk); 102 spin_unlock_irqrestore(&clocks_lock, flags); 103 } 104 105 return 0; 106 } 107 EXPORT_SYMBOL(clk_enable); 108 109 void clk_disable(struct clk *clk) 110 { 111 unsigned long flags; 112 113 if (clk) { 114 WARN_ON(clk->enabled == 0); 115 spin_lock_irqsave(&clocks_lock, flags); 116 if (--clk->enabled == 0) 117 clk->ops->disable(clk); 118 spin_unlock_irqrestore(&clocks_lock, flags); 119 } 120 } 121 EXPORT_SYMBOL(clk_disable); 122 123 unsigned long clk_get_rate(struct clk *clk) 124 { 125 if (clk && clk->ops && clk->ops->get_rate) 126 return clk->ops->get_rate(clk); 127 128 return 0; 129 } 130 EXPORT_SYMBOL(clk_get_rate); 131 132 const struct clkops clk_gpio27_ops = { 133 .enable = clk_gpio27_enable, 134 .disable = clk_gpio27_disable, 135 }; 136 137 const struct clkops clk_cpu_ops = { 138 .enable = clk_cpu_enable, 139 .disable = clk_cpu_disable, 140 .get_rate = clk_cpu_get_rate, 141 }; 142 143 static DEFINE_CLK(gpio27, &clk_gpio27_ops); 144 145 static DEFINE_CLK(cpu, &clk_cpu_ops); 146 147 static unsigned long clk_36864_get_rate(struct clk *clk) 148 { 149 return 3686400; 150 } 151 152 static struct clkops clk_36864_ops = { 153 .enable = clk_cpu_enable, 154 .disable = clk_cpu_disable, 155 .get_rate = clk_36864_get_rate, 156 }; 157 158 static DEFINE_CLK(36864, &clk_36864_ops); 159 160 static struct clk_lookup sa11xx_clkregs[] = { 161 CLKDEV_INIT("sa1111.0", NULL, &clk_gpio27), 162 CLKDEV_INIT("sa1100-rtc", NULL, NULL), 163 CLKDEV_INIT("sa11x0-fb", NULL, &clk_cpu), 164 CLKDEV_INIT("sa11x0-pcmcia", NULL, &clk_cpu), 165 /* sa1111 names devices using internal offsets, PCMCIA is at 0x1800 */ 166 CLKDEV_INIT("1800", NULL, &clk_cpu), 167 CLKDEV_INIT(NULL, "OSTIMER0", &clk_36864), 168 }; 169 170 int __init sa11xx_clk_init(void) 171 { 172 clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs)); 173 return 0; 174 } 175