171b9114dSArnd Bergmann /* SPDX-License-Identifier: GPL-2.0-only */ 271b9114dSArnd Bergmann /* 371b9114dSArnd Bergmann * Copyright 2008 Openmoko, Inc. 471b9114dSArnd Bergmann * Copyright 2008 Simtec Electronics 571b9114dSArnd Bergmann * http://armlinux.simtec.co.uk/ 671b9114dSArnd Bergmann * Ben Dooks <ben@simtec.co.uk> 771b9114dSArnd Bergmann * 871b9114dSArnd Bergmann * S3C - USB2.0 Highspeed/OtG device PHY registers 971b9114dSArnd Bergmann */ 1071b9114dSArnd Bergmann 1171b9114dSArnd Bergmann /* Note, this is a separate header file as some of the clock framework 1271b9114dSArnd Bergmann * needs to touch this if the clk_48m is used as the USB OHCI or other 1371b9114dSArnd Bergmann * peripheral source. 1471b9114dSArnd Bergmann */ 1571b9114dSArnd Bergmann 1671b9114dSArnd Bergmann #ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H 1771b9114dSArnd Bergmann #define __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H __FILE__ 1871b9114dSArnd Bergmann 1971b9114dSArnd Bergmann /* S3C64XX_PA_USB_HSPHY */ 2071b9114dSArnd Bergmann 2171b9114dSArnd Bergmann #define S3C_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY) 2271b9114dSArnd Bergmann 2371b9114dSArnd Bergmann #define S3C_PHYPWR S3C_HSOTG_PHYREG(0x00) 2471b9114dSArnd Bergmann #define S3C_PHYPWR_NORMAL_MASK (0x19 << 0) 2571b9114dSArnd Bergmann #define S3C_PHYPWR_OTG_DISABLE (1 << 4) 2671b9114dSArnd Bergmann #define S3C_PHYPWR_ANALOG_POWERDOWN (1 << 3) 2771b9114dSArnd Bergmann #define SRC_PHYPWR_FORCE_SUSPEND (1 << 1) 2871b9114dSArnd Bergmann 2971b9114dSArnd Bergmann #define S3C_PHYCLK S3C_HSOTG_PHYREG(0x04) 3071b9114dSArnd Bergmann #define S3C_PHYCLK_MODE_USB11 (1 << 6) 3171b9114dSArnd Bergmann #define S3C_PHYCLK_EXT_OSC (1 << 5) 3271b9114dSArnd Bergmann #define S3C_PHYCLK_CLK_FORCE (1 << 4) 3371b9114dSArnd Bergmann #define S3C_PHYCLK_ID_PULL (1 << 2) 3471b9114dSArnd Bergmann #define S3C_PHYCLK_CLKSEL_MASK (0x3 << 0) 3571b9114dSArnd Bergmann #define S3C_PHYCLK_CLKSEL_SHIFT (0) 3671b9114dSArnd Bergmann #define S3C_PHYCLK_CLKSEL_48M (0x0 << 0) 3771b9114dSArnd Bergmann #define S3C_PHYCLK_CLKSEL_12M (0x2 << 0) 3871b9114dSArnd Bergmann #define S3C_PHYCLK_CLKSEL_24M (0x3 << 0) 3971b9114dSArnd Bergmann 4071b9114dSArnd Bergmann #define S3C_RSTCON S3C_HSOTG_PHYREG(0x08) 4171b9114dSArnd Bergmann #define S3C_RSTCON_PHYCLK (1 << 2) 4271b9114dSArnd Bergmann #define S3C_RSTCON_HCLK (1 << 1) 4371b9114dSArnd Bergmann #define S3C_RSTCON_PHY (1 << 0) 4471b9114dSArnd Bergmann 4571b9114dSArnd Bergmann #define S3C_PHYTUNE S3C_HSOTG_PHYREG(0x20) 4671b9114dSArnd Bergmann 4771b9114dSArnd Bergmann #endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H */ 48