1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright 2008 Openmoko, Inc.
4  * Copyright 2008 Simtec Electronics
5  *      http://armlinux.simtec.co.uk/
6  *      Ben Dooks <ben@simtec.co.uk>
7  *
8  * S3C64XX - syscon power and sleep control registers
9 */
10 
11 #ifndef __MACH_S3C64XX_REGS_SYSCON_POWER_H
12 #define __MACH_S3C64XX_REGS_SYSCON_POWER_H __FILE__
13 
14 #define S3C64XX_PWR_CFG				S3C_SYSREG(0x804)
15 
16 #define S3C64XX_PWRCFG_OSC_OTG_DISABLE		(1 << 17)
17 #define S3C64XX_PWRCFG_MMC2_DISABLE		(1 << 16)
18 #define S3C64XX_PWRCFG_MMC1_DISABLE		(1 << 15)
19 #define S3C64XX_PWRCFG_MMC0_DISABLE		(1 << 14)
20 #define S3C64XX_PWRCFG_HSI_DISABLE		(1 << 13)
21 #define S3C64XX_PWRCFG_TS_DISABLE		(1 << 12)
22 #define S3C64XX_PWRCFG_RTC_TICK_DISABLE		(1 << 11)
23 #define S3C64XX_PWRCFG_RTC_ALARM_DISABLE	(1 << 10)
24 #define S3C64XX_PWRCFG_MSM_DISABLE		(1 << 9)
25 #define S3C64XX_PWRCFG_KEY_DISABLE		(1 << 8)
26 #define S3C64XX_PWRCFG_BATF_DISABLE		(1 << 7)
27 
28 #define S3C64XX_PWRCFG_CFG_WFI_MASK		(0x3 << 5)
29 #define S3C64XX_PWRCFG_CFG_WFI_SHIFT		(5)
30 #define S3C64XX_PWRCFG_CFG_WFI_IGNORE		(0x0 << 5)
31 #define S3C64XX_PWRCFG_CFG_WFI_IDLE		(0x1 << 5)
32 #define S3C64XX_PWRCFG_CFG_WFI_STOP		(0x2 << 5)
33 #define S3C64XX_PWRCFG_CFG_WFI_SLEEP		(0x3 << 5)
34 
35 #define S3C64XX_PWRCFG_CFG_BATFLT_MASK		(0x3 << 3)
36 #define S3C64XX_PWRCFG_CFG_BATFLT_SHIFT		(3)
37 #define S3C64XX_PWRCFG_CFG_BATFLT_IGNORE	(0x0 << 3)
38 #define S3C64XX_PWRCFG_CFG_BATFLT_IRQ		(0x1 << 3)
39 #define S3C64XX_PWRCFG_CFG_BATFLT_SLEEP		(0x3 << 3)
40 
41 #define S3C64XX_PWRCFG_CFG_BAT_WAKE		(1 << 2)
42 #define S3C64XX_PWRCFG_OSC27_EN			(1 << 0)
43 
44 #define S3C64XX_EINT_MASK			S3C_SYSREG(0x808)
45 
46 #define S3C64XX_NORMAL_CFG			S3C_SYSREG(0x810)
47 
48 #define S3C64XX_NORMALCFG_IROM_ON		(1 << 30)
49 #define S3C64XX_NORMALCFG_DOMAIN_ETM_ON		(1 << 16)
50 #define S3C64XX_NORMALCFG_DOMAIN_S_ON		(1 << 15)
51 #define S3C64XX_NORMALCFG_DOMAIN_F_ON		(1 << 14)
52 #define S3C64XX_NORMALCFG_DOMAIN_P_ON		(1 << 13)
53 #define S3C64XX_NORMALCFG_DOMAIN_I_ON		(1 << 12)
54 #define S3C64XX_NORMALCFG_DOMAIN_G_ON		(1 << 10)
55 #define S3C64XX_NORMALCFG_DOMAIN_V_ON		(1 << 9)
56 
57 #define S3C64XX_STOP_CFG			S3C_SYSREG(0x814)
58 
59 #define S3C64XX_STOPCFG_MEMORY_ARM_ON		(1 << 29)
60 #define S3C64XX_STOPCFG_TOP_MEMORY_ON		(1 << 20)
61 #define S3C64XX_STOPCFG_ARM_LOGIC_ON		(1 << 17)
62 #define S3C64XX_STOPCFG_TOP_LOGIC_ON		(1 << 8)
63 #define S3C64XX_STOPCFG_OSC_EN			(1 << 0)
64 
65 #define S3C64XX_SLEEP_CFG			S3C_SYSREG(0x818)
66 
67 #define S3C64XX_SLEEPCFG_OSC_EN			(1 << 0)
68 
69 #define S3C64XX_STOP_MEM_CFG			S3C_SYSREG(0x81c)
70 
71 #define S3C64XX_STOPMEMCFG_MODEMIF_RETAIN	(1 << 6)
72 #define S3C64XX_STOPMEMCFG_HOSTIF_RETAIN	(1 << 5)
73 #define S3C64XX_STOPMEMCFG_OTG_RETAIN		(1 << 4)
74 #define S3C64XX_STOPMEMCFG_HSMCC_RETAIN		(1 << 3)
75 #define S3C64XX_STOPMEMCFG_IROM_RETAIN		(1 << 2)
76 #define S3C64XX_STOPMEMCFG_IRDA_RETAIN		(1 << 1)
77 #define S3C64XX_STOPMEMCFG_NFCON_RETAIN		(1 << 0)
78 
79 #define S3C64XX_OSC_STABLE			S3C_SYSREG(0x824)
80 #define S3C64XX_PWR_STABLE			S3C_SYSREG(0x828)
81 
82 #define S3C64XX_WAKEUP_STAT			S3C_SYSREG(0x908)
83 
84 #define S3C64XX_WAKEUPSTAT_MMC2			(1 << 11)
85 #define S3C64XX_WAKEUPSTAT_MMC1			(1 << 10)
86 #define S3C64XX_WAKEUPSTAT_MMC0			(1 << 9)
87 #define S3C64XX_WAKEUPSTAT_HSI			(1 << 8)
88 #define S3C64XX_WAKEUPSTAT_BATFLT		(1 << 6)
89 #define S3C64XX_WAKEUPSTAT_MSM			(1 << 5)
90 #define S3C64XX_WAKEUPSTAT_KEY			(1 << 4)
91 #define S3C64XX_WAKEUPSTAT_TS			(1 << 3)
92 #define S3C64XX_WAKEUPSTAT_RTC_TICK		(1 << 2)
93 #define S3C64XX_WAKEUPSTAT_RTC_ALARM		(1 << 1)
94 #define S3C64XX_WAKEUPSTAT_EINT			(1 << 0)
95 
96 #define S3C64XX_BLK_PWR_STAT			S3C_SYSREG(0x90c)
97 
98 #define S3C64XX_BLKPWRSTAT_G			(1 << 7)
99 #define S3C64XX_BLKPWRSTAT_ETM			(1 << 6)
100 #define S3C64XX_BLKPWRSTAT_S			(1 << 5)
101 #define S3C64XX_BLKPWRSTAT_F			(1 << 4)
102 #define S3C64XX_BLKPWRSTAT_P			(1 << 3)
103 #define S3C64XX_BLKPWRSTAT_I			(1 << 2)
104 #define S3C64XX_BLKPWRSTAT_V			(1 << 1)
105 #define S3C64XX_BLKPWRSTAT_TOP			(1 << 0)
106 
107 #define S3C64XX_INFORM0				S3C_SYSREG(0xA00)
108 #define S3C64XX_INFORM1				S3C_SYSREG(0xA04)
109 #define S3C64XX_INFORM2				S3C_SYSREG(0xA08)
110 #define S3C64XX_INFORM3				S3C_SYSREG(0xA0C)
111 
112 #endif /* __MACH_S3C64XX_REGS_SYSCON_POWER_H */
113