1c6ff132dSArnd Bergmann /* SPDX-License-Identifier: GPL-2.0 */ 2c6ff132dSArnd Bergmann /* 3c6ff132dSArnd Bergmann * Copyright 2008 Openmoko, Inc. 4c6ff132dSArnd Bergmann * Copyright 2008 Simtec Electronics 5c6ff132dSArnd Bergmann * Ben Dooks <ben@simtec.co.uk> 6c6ff132dSArnd Bergmann * http://armlinux.simtec.co.uk/ 7c6ff132dSArnd Bergmann * 8c6ff132dSArnd Bergmann * S3C64XX - PM core support for arch/arm/plat-s3c/pm.c 9c6ff132dSArnd Bergmann */ 10c6ff132dSArnd Bergmann 11c6ff132dSArnd Bergmann #ifndef __MACH_S3C64XX_PM_CORE_H 12c6ff132dSArnd Bergmann #define __MACH_S3C64XX_PM_CORE_H __FILE__ 13c6ff132dSArnd Bergmann 14c6ff132dSArnd Bergmann #include <linux/serial_s3c.h> 15c6ff132dSArnd Bergmann #include <linux/delay.h> 16c6ff132dSArnd Bergmann 17c6ff132dSArnd Bergmann #include "regs-gpio.h" 18c6ff132dSArnd Bergmann #include "regs-clock.h" 19c6ff132dSArnd Bergmann #include "map.h" 20c6ff132dSArnd Bergmann 21c6ff132dSArnd Bergmann static inline void s3c_pm_debug_init_uart(void) 22c6ff132dSArnd Bergmann { 23c6ff132dSArnd Bergmann #ifdef CONFIG_SAMSUNG_PM_DEBUG 24c6ff132dSArnd Bergmann u32 tmp = __raw_readl(S3C_PCLK_GATE); 25c6ff132dSArnd Bergmann 26c6ff132dSArnd Bergmann /* As a note, since the S3C64XX UARTs generally have multiple 27c6ff132dSArnd Bergmann * clock sources, we simply enable PCLK at the moment and hope 28c6ff132dSArnd Bergmann * that the resume settings for the UART are suitable for the 29c6ff132dSArnd Bergmann * use with PCLK. 30c6ff132dSArnd Bergmann */ 31c6ff132dSArnd Bergmann 32c6ff132dSArnd Bergmann tmp |= S3C_CLKCON_PCLK_UART0; 33c6ff132dSArnd Bergmann tmp |= S3C_CLKCON_PCLK_UART1; 34c6ff132dSArnd Bergmann tmp |= S3C_CLKCON_PCLK_UART2; 35c6ff132dSArnd Bergmann tmp |= S3C_CLKCON_PCLK_UART3; 36c6ff132dSArnd Bergmann 37c6ff132dSArnd Bergmann __raw_writel(tmp, S3C_PCLK_GATE); 38c6ff132dSArnd Bergmann udelay(10); 39c6ff132dSArnd Bergmann #endif 40c6ff132dSArnd Bergmann } 41c6ff132dSArnd Bergmann 42c6ff132dSArnd Bergmann static inline void s3c_pm_arch_prepare_irqs(void) 43c6ff132dSArnd Bergmann { 44c6ff132dSArnd Bergmann /* VIC should have already been taken care of */ 45c6ff132dSArnd Bergmann 46c6ff132dSArnd Bergmann /* clear any pending EINT0 interrupts */ 47c6ff132dSArnd Bergmann __raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND); 48c6ff132dSArnd Bergmann } 49c6ff132dSArnd Bergmann 50c6ff132dSArnd Bergmann static inline void s3c_pm_arch_stop_clocks(void) 51c6ff132dSArnd Bergmann { 52c6ff132dSArnd Bergmann } 53c6ff132dSArnd Bergmann 54c6ff132dSArnd Bergmann static inline void s3c_pm_arch_show_resume_irqs(void) 55c6ff132dSArnd Bergmann { 56c6ff132dSArnd Bergmann } 57c6ff132dSArnd Bergmann 58c6ff132dSArnd Bergmann /* make these defines, we currently do not have any need to change 59c6ff132dSArnd Bergmann * the IRQ wake controls depending on the CPU we are running on */ 60c6ff132dSArnd Bergmann #ifdef CONFIG_PM_SLEEP 61c6ff132dSArnd Bergmann #define s3c_irqwake_eintallow ((1 << 28) - 1) 62c6ff132dSArnd Bergmann #define s3c_irqwake_intallow (~0) 63c6ff132dSArnd Bergmann #else 64c6ff132dSArnd Bergmann #define s3c_irqwake_eintallow 0 65c6ff132dSArnd Bergmann #define s3c_irqwake_intallow 0 66c6ff132dSArnd Bergmann #endif 67c6ff132dSArnd Bergmann 68c6ff132dSArnd Bergmann static inline void s3c_pm_restored_gpios(void) 69c6ff132dSArnd Bergmann { 70c6ff132dSArnd Bergmann /* ensure sleep mode has been cleared from the system */ 71c6ff132dSArnd Bergmann 72c6ff132dSArnd Bergmann __raw_writel(0, S3C64XX_SLPEN); 73c6ff132dSArnd Bergmann } 74c6ff132dSArnd Bergmann 75c6ff132dSArnd Bergmann static inline void samsung_pm_saved_gpios(void) 76c6ff132dSArnd Bergmann { 77c6ff132dSArnd Bergmann /* turn on the sleep mode and keep it there, as it seems that during 78c6ff132dSArnd Bergmann * suspend the xCON registers get re-set and thus you can end up with 79c6ff132dSArnd Bergmann * problems between going to sleep and resuming. 80c6ff132dSArnd Bergmann */ 81c6ff132dSArnd Bergmann 82c6ff132dSArnd Bergmann __raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN); 83c6ff132dSArnd Bergmann } 84c6ff132dSArnd Bergmann #endif /* __MACH_S3C64XX_PM_CORE_H */ 85