1c6ff132dSArnd Bergmann /* SPDX-License-Identifier: GPL-2.0 */ 2c6ff132dSArnd Bergmann /* 3c6ff132dSArnd Bergmann * Copyright 2008 Openmoko, Inc. 4c6ff132dSArnd Bergmann * Copyright 2008 Simtec Electronics 5c6ff132dSArnd Bergmann * Ben Dooks <ben@simtec.co.uk> 6c6ff132dSArnd Bergmann * http://armlinux.simtec.co.uk/ 7c6ff132dSArnd Bergmann * 8c6ff132dSArnd Bergmann * S3C64XX - PM core support for arch/arm/plat-s3c/pm.c 9c6ff132dSArnd Bergmann */ 10c6ff132dSArnd Bergmann 11c6ff132dSArnd Bergmann #ifndef __MACH_S3C64XX_PM_CORE_H 12c6ff132dSArnd Bergmann #define __MACH_S3C64XX_PM_CORE_H __FILE__ 13c6ff132dSArnd Bergmann 14c6ff132dSArnd Bergmann #include <linux/serial_s3c.h> 15c6ff132dSArnd Bergmann #include <linux/delay.h> 16c6ff132dSArnd Bergmann 17c6ff132dSArnd Bergmann #include "regs-gpio.h" 18c6ff132dSArnd Bergmann #include "regs-clock.h" 19c6ff132dSArnd Bergmann #include "map.h" 20c6ff132dSArnd Bergmann s3c_pm_debug_init_uart(void)21c6ff132dSArnd Bergmannstatic inline void s3c_pm_debug_init_uart(void) 22c6ff132dSArnd Bergmann { 23c6ff132dSArnd Bergmann } 24c6ff132dSArnd Bergmann s3c_pm_arch_prepare_irqs(void)25c6ff132dSArnd Bergmannstatic inline void s3c_pm_arch_prepare_irqs(void) 26c6ff132dSArnd Bergmann { 27c6ff132dSArnd Bergmann /* VIC should have already been taken care of */ 28c6ff132dSArnd Bergmann 29c6ff132dSArnd Bergmann /* clear any pending EINT0 interrupts */ 30c6ff132dSArnd Bergmann __raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND); 31c6ff132dSArnd Bergmann } 32c6ff132dSArnd Bergmann s3c_pm_arch_stop_clocks(void)33c6ff132dSArnd Bergmannstatic inline void s3c_pm_arch_stop_clocks(void) 34c6ff132dSArnd Bergmann { 35c6ff132dSArnd Bergmann } 36c6ff132dSArnd Bergmann s3c_pm_arch_show_resume_irqs(void)37c6ff132dSArnd Bergmannstatic inline void s3c_pm_arch_show_resume_irqs(void) 38c6ff132dSArnd Bergmann { 39c6ff132dSArnd Bergmann } 40c6ff132dSArnd Bergmann 41c6ff132dSArnd Bergmann /* make these defines, we currently do not have any need to change 42c6ff132dSArnd Bergmann * the IRQ wake controls depending on the CPU we are running on */ 43c6ff132dSArnd Bergmann #ifdef CONFIG_PM_SLEEP 44c6ff132dSArnd Bergmann #define s3c_irqwake_eintallow ((1 << 28) - 1) 45c6ff132dSArnd Bergmann #define s3c_irqwake_intallow (~0) 46c6ff132dSArnd Bergmann #else 47c6ff132dSArnd Bergmann #define s3c_irqwake_eintallow 0 48c6ff132dSArnd Bergmann #define s3c_irqwake_intallow 0 49c6ff132dSArnd Bergmann #endif 50c6ff132dSArnd Bergmann s3c_pm_restored_gpios(void)51c6ff132dSArnd Bergmannstatic inline void s3c_pm_restored_gpios(void) 52c6ff132dSArnd Bergmann { 53c6ff132dSArnd Bergmann /* ensure sleep mode has been cleared from the system */ 54c6ff132dSArnd Bergmann 55c6ff132dSArnd Bergmann __raw_writel(0, S3C64XX_SLPEN); 56c6ff132dSArnd Bergmann } 57c6ff132dSArnd Bergmann samsung_pm_saved_gpios(void)58c6ff132dSArnd Bergmannstatic inline void samsung_pm_saved_gpios(void) 59c6ff132dSArnd Bergmann { 60c6ff132dSArnd Bergmann /* turn on the sleep mode and keep it there, as it seems that during 61c6ff132dSArnd Bergmann * suspend the xCON registers get re-set and thus you can end up with 62c6ff132dSArnd Bergmann * problems between going to sleep and resuming. 63c6ff132dSArnd Bergmann */ 64c6ff132dSArnd Bergmann 65c6ff132dSArnd Bergmann __raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN); 66c6ff132dSArnd Bergmann } 67c6ff132dSArnd Bergmann #endif /* __MACH_S3C64XX_PM_CORE_H */ 68