1 /* 2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd 3 * Author: Tony Xie <tony.xie@rock-chips.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 */ 15 16 #include <linux/init.h> 17 #include <linux/io.h> 18 #include <linux/kernel.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 #include <linux/regmap.h> 22 #include <linux/suspend.h> 23 #include <linux/mfd/syscon.h> 24 #include <linux/regulator/machine.h> 25 26 #include <asm/cacheflush.h> 27 #include <asm/tlbflush.h> 28 #include <asm/suspend.h> 29 30 #include "pm.h" 31 32 /* These enum are option of low power mode */ 33 enum { 34 ROCKCHIP_ARM_OFF_LOGIC_NORMAL = 0, 35 ROCKCHIP_ARM_OFF_LOGIC_DEEP = 1, 36 }; 37 38 struct rockchip_pm_data { 39 const struct platform_suspend_ops *ops; 40 int (*init)(struct device_node *np); 41 }; 42 43 static void __iomem *rk3288_bootram_base; 44 static phys_addr_t rk3288_bootram_phy; 45 46 static struct regmap *pmu_regmap; 47 static struct regmap *sgrf_regmap; 48 static struct regmap *grf_regmap; 49 50 static u32 rk3288_pmu_pwr_mode_con; 51 static u32 rk3288_sgrf_soc_con0; 52 static u32 rk3288_sgrf_cpu_con0; 53 54 static inline u32 rk3288_l2_config(void) 55 { 56 u32 l2ctlr; 57 58 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (l2ctlr)); 59 return l2ctlr; 60 } 61 62 static void rk3288_config_bootdata(void) 63 { 64 rkpm_bootdata_cpusp = rk3288_bootram_phy + (SZ_4K - 8); 65 rkpm_bootdata_cpu_code = virt_to_phys(cpu_resume); 66 67 rkpm_bootdata_l2ctlr_f = 1; 68 rkpm_bootdata_l2ctlr = rk3288_l2_config(); 69 } 70 71 #define GRF_UOC0_CON0 0x320 72 #define GRF_UOC1_CON0 0x334 73 #define GRF_UOC2_CON0 0x348 74 #define GRF_SIDDQ BIT(13) 75 76 static bool rk3288_slp_disable_osc(void) 77 { 78 static const u32 reg_offset[] = { GRF_UOC0_CON0, GRF_UOC1_CON0, 79 GRF_UOC2_CON0 }; 80 u32 reg, i; 81 82 /* 83 * if any usb phy is still on(GRF_SIDDQ==0), that means we need the 84 * function of usb wakeup, so do not switch to 32khz, since the usb phy 85 * clk does not connect to 32khz osc 86 */ 87 for (i = 0; i < ARRAY_SIZE(reg_offset); i++) { 88 regmap_read(grf_regmap, reg_offset[i], ®); 89 if (!(reg & GRF_SIDDQ)) 90 return false; 91 } 92 93 return true; 94 } 95 96 static void rk3288_slp_mode_set(int level) 97 { 98 u32 mode_set, mode_set1; 99 bool osc_disable = rk3288_slp_disable_osc(); 100 101 regmap_read(sgrf_regmap, RK3288_SGRF_CPU_CON0, &rk3288_sgrf_cpu_con0); 102 regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0); 103 104 regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON, 105 &rk3288_pmu_pwr_mode_con); 106 107 /* 108 * SGRF_FAST_BOOT_EN - system to boot from FAST_BOOT_ADDR 109 * PCLK_WDT_GATE - disable WDT during suspend. 110 */ 111 regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0, 112 SGRF_PCLK_WDT_GATE | SGRF_FAST_BOOT_EN 113 | SGRF_PCLK_WDT_GATE_WRITE | SGRF_FAST_BOOT_EN_WRITE); 114 115 /* 116 * The dapswjdp can not auto reset before resume, that cause it may 117 * access some illegal address during resume. Let's disable it before 118 * suspend, and the MASKROM will enable it back. 119 */ 120 regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0, SGRF_DAPDEVICEEN_WRITE); 121 122 /* booting address of resuming system is from this register value */ 123 regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR, 124 rk3288_bootram_phy); 125 126 mode_set = BIT(PMU_GLOBAL_INT_DISABLE) | BIT(PMU_L2FLUSH_EN) | 127 BIT(PMU_SREF0_ENTER_EN) | BIT(PMU_SREF1_ENTER_EN) | 128 BIT(PMU_DDR0_GATING_EN) | BIT(PMU_DDR1_GATING_EN) | 129 BIT(PMU_PWR_MODE_EN) | BIT(PMU_CHIP_PD_EN) | 130 BIT(PMU_SCU_EN); 131 132 mode_set1 = BIT(PMU_CLR_CORE) | BIT(PMU_CLR_CPUP); 133 134 if (level == ROCKCHIP_ARM_OFF_LOGIC_DEEP) { 135 /* arm off, logic deep sleep */ 136 mode_set |= BIT(PMU_BUS_PD_EN) | BIT(PMU_PMU_USE_LF) | 137 BIT(PMU_DDR1IO_RET_EN) | BIT(PMU_DDR0IO_RET_EN) | 138 BIT(PMU_ALIVE_USE_LF) | BIT(PMU_PLL_PD_EN); 139 140 if (osc_disable) 141 mode_set |= BIT(PMU_OSC_24M_DIS); 142 143 mode_set1 |= BIT(PMU_CLR_ALIVE) | BIT(PMU_CLR_BUS) | 144 BIT(PMU_CLR_PERI) | BIT(PMU_CLR_DMA); 145 146 regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1, 147 PMU_ARMINT_WAKEUP_EN); 148 149 /* 150 * In deep suspend we use PMU_PMU_USE_LF to let the rk3288 151 * switch its main clock supply to the alternative 32kHz 152 * source. Therefore set 30ms on a 32kHz clock for pmic 153 * stabilization. Similar 30ms on 24MHz for the other 154 * mode below. 155 */ 156 regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 32 * 30); 157 158 /* only wait for stabilization, if we turned the osc off */ 159 regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, 160 osc_disable ? 32 * 30 : 0); 161 } else { 162 /* 163 * arm off, logic normal 164 * if pmu_clk_core_src_gate_en is not set, 165 * wakeup will be error 166 */ 167 mode_set |= BIT(PMU_CLK_CORE_SRC_GATE_EN); 168 169 regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1, 170 PMU_ARMINT_WAKEUP_EN | PMU_GPIOINT_WAKEUP_EN); 171 172 /* 30ms on a 24MHz clock for pmic stabilization */ 173 regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 24000 * 30); 174 175 /* oscillator is still running, so no need to wait */ 176 regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, 0); 177 } 178 179 regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON, mode_set); 180 regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON1, mode_set1); 181 } 182 183 static void rk3288_slp_mode_set_resume(void) 184 { 185 regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0, 186 rk3288_sgrf_cpu_con0 | SGRF_DAPDEVICEEN_WRITE); 187 188 regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON, 189 rk3288_pmu_pwr_mode_con); 190 191 regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0, 192 rk3288_sgrf_soc_con0 | SGRF_PCLK_WDT_GATE_WRITE 193 | SGRF_FAST_BOOT_EN_WRITE); 194 } 195 196 static int rockchip_lpmode_enter(unsigned long arg) 197 { 198 flush_cache_all(); 199 200 cpu_do_idle(); 201 202 pr_err("%s: Failed to suspend\n", __func__); 203 204 return 1; 205 } 206 207 static int rk3288_suspend_enter(suspend_state_t state) 208 { 209 local_fiq_disable(); 210 211 rk3288_slp_mode_set(ROCKCHIP_ARM_OFF_LOGIC_NORMAL); 212 213 cpu_suspend(0, rockchip_lpmode_enter); 214 215 rk3288_slp_mode_set_resume(); 216 217 local_fiq_enable(); 218 219 return 0; 220 } 221 222 static int rk3288_suspend_prepare(void) 223 { 224 return regulator_suspend_prepare(PM_SUSPEND_MEM); 225 } 226 227 static void rk3288_suspend_finish(void) 228 { 229 if (regulator_suspend_finish()) 230 pr_err("%s: Suspend finish failed\n", __func__); 231 } 232 233 static int rk3288_suspend_init(struct device_node *np) 234 { 235 struct device_node *sram_np; 236 struct resource res; 237 int ret; 238 239 pmu_regmap = syscon_node_to_regmap(np); 240 if (IS_ERR(pmu_regmap)) { 241 pr_err("%s: could not find pmu regmap\n", __func__); 242 return PTR_ERR(pmu_regmap); 243 } 244 245 sgrf_regmap = syscon_regmap_lookup_by_compatible( 246 "rockchip,rk3288-sgrf"); 247 if (IS_ERR(sgrf_regmap)) { 248 pr_err("%s: could not find sgrf regmap\n", __func__); 249 return PTR_ERR(sgrf_regmap); 250 } 251 252 grf_regmap = syscon_regmap_lookup_by_compatible( 253 "rockchip,rk3288-grf"); 254 if (IS_ERR(grf_regmap)) { 255 pr_err("%s: could not find grf regmap\n", __func__); 256 return PTR_ERR(grf_regmap); 257 } 258 259 sram_np = of_find_compatible_node(NULL, NULL, 260 "rockchip,rk3288-pmu-sram"); 261 if (!sram_np) { 262 pr_err("%s: could not find bootram dt node\n", __func__); 263 return -ENODEV; 264 } 265 266 rk3288_bootram_base = of_iomap(sram_np, 0); 267 if (!rk3288_bootram_base) { 268 pr_err("%s: could not map bootram base\n", __func__); 269 return -ENOMEM; 270 } 271 272 ret = of_address_to_resource(sram_np, 0, &res); 273 if (ret) { 274 pr_err("%s: could not get bootram phy addr\n", __func__); 275 return ret; 276 } 277 rk3288_bootram_phy = res.start; 278 279 of_node_put(sram_np); 280 281 rk3288_config_bootdata(); 282 283 /* copy resume code and data to bootsram */ 284 memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume, 285 rk3288_bootram_sz); 286 287 return 0; 288 } 289 290 static const struct platform_suspend_ops rk3288_suspend_ops = { 291 .enter = rk3288_suspend_enter, 292 .valid = suspend_valid_only_mem, 293 .prepare = rk3288_suspend_prepare, 294 .finish = rk3288_suspend_finish, 295 }; 296 297 static const struct rockchip_pm_data rk3288_pm_data __initconst = { 298 .ops = &rk3288_suspend_ops, 299 .init = rk3288_suspend_init, 300 }; 301 302 static const struct of_device_id rockchip_pmu_of_device_ids[] __initconst = { 303 { 304 .compatible = "rockchip,rk3288-pmu", 305 .data = &rk3288_pm_data, 306 }, 307 { /* sentinel */ }, 308 }; 309 310 void __init rockchip_suspend_init(void) 311 { 312 const struct rockchip_pm_data *pm_data; 313 const struct of_device_id *match; 314 struct device_node *np; 315 int ret; 316 317 np = of_find_matching_node_and_match(NULL, rockchip_pmu_of_device_ids, 318 &match); 319 if (!match) { 320 pr_err("Failed to find PMU node\n"); 321 return; 322 } 323 pm_data = (struct rockchip_pm_data *) match->data; 324 325 if (pm_data->init) { 326 ret = pm_data->init(np); 327 328 if (ret) { 329 pr_err("%s: matches init error %d\n", __func__, ret); 330 return; 331 } 332 } 333 334 suspend_set_ops(pm_data->ops); 335 } 336