1 /* 2 * Copyright (c) 2013 MundoReader S.L. 3 * Author: Heiko Stuebner <heiko@sntech.de> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/delay.h> 17 #include <linux/init.h> 18 #include <linux/smp.h> 19 #include <linux/io.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/regmap.h> 23 #include <linux/mfd/syscon.h> 24 25 #include <linux/reset.h> 26 #include <linux/cpu.h> 27 #include <asm/cacheflush.h> 28 #include <asm/cp15.h> 29 #include <asm/smp_scu.h> 30 #include <asm/smp_plat.h> 31 #include <asm/mach/map.h> 32 33 #include "core.h" 34 35 static void __iomem *scu_base_addr; 36 static void __iomem *sram_base_addr; 37 static int ncores; 38 39 #define PMU_PWRDN_CON 0x08 40 #define PMU_PWRDN_ST 0x0c 41 42 #define PMU_PWRDN_SCU 4 43 44 static struct regmap *pmu; 45 46 static int pmu_power_domain_is_on(int pd) 47 { 48 u32 val; 49 int ret; 50 51 ret = regmap_read(pmu, PMU_PWRDN_ST, &val); 52 if (ret < 0) 53 return ret; 54 55 return !(val & BIT(pd)); 56 } 57 58 struct reset_control *rockchip_get_core_reset(int cpu) 59 { 60 struct device *dev = get_cpu_device(cpu); 61 struct device_node *np; 62 63 /* The cpu device is only available after the initial core bringup */ 64 if (dev) 65 np = dev->of_node; 66 else 67 np = of_get_cpu_node(cpu, 0); 68 69 return of_reset_control_get(np, NULL); 70 } 71 72 static int pmu_set_power_domain(int pd, bool on) 73 { 74 u32 val = (on) ? 0 : BIT(pd); 75 int ret; 76 77 /* 78 * We need to soft reset the cpu when we turn off the cpu power domain, 79 * or else the active processors might be stalled when the individual 80 * processor is powered down. 81 */ 82 if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) { 83 struct reset_control *rstc = rockchip_get_core_reset(pd); 84 85 if (IS_ERR(rstc)) { 86 pr_err("%s: could not get reset control for core %d\n", 87 __func__, pd); 88 return PTR_ERR(rstc); 89 } 90 91 if (on) 92 reset_control_deassert(rstc); 93 else 94 reset_control_assert(rstc); 95 96 reset_control_put(rstc); 97 } 98 99 ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val); 100 if (ret < 0) { 101 pr_err("%s: could not update power domain\n", __func__); 102 return ret; 103 } 104 105 ret = -1; 106 while (ret != on) { 107 ret = pmu_power_domain_is_on(pd); 108 if (ret < 0) { 109 pr_err("%s: could not read power domain state\n", 110 __func__); 111 return ret; 112 } 113 } 114 115 return 0; 116 } 117 118 /* 119 * Handling of CPU cores 120 */ 121 122 static int __cpuinit rockchip_boot_secondary(unsigned int cpu, 123 struct task_struct *idle) 124 { 125 int ret; 126 127 if (!sram_base_addr || !pmu) { 128 pr_err("%s: sram or pmu missing for cpu boot\n", __func__); 129 return -ENXIO; 130 } 131 132 if (cpu >= ncores) { 133 pr_err("%s: cpu %d outside maximum number of cpus %d\n", 134 __func__, cpu, ncores); 135 return -ENXIO; 136 } 137 138 /* start the core */ 139 ret = pmu_set_power_domain(0 + cpu, true); 140 if (ret < 0) 141 return ret; 142 143 if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) { 144 /* We communicate with the bootrom to active the cpus other 145 * than cpu0, after a blob of initialize code, they will 146 * stay at wfe state, once they are actived, they will check 147 * the mailbox: 148 * sram_base_addr + 4: 0xdeadbeaf 149 * sram_base_addr + 8: start address for pc 150 * */ 151 udelay(10); 152 writel(virt_to_phys(rockchip_secondary_startup), 153 sram_base_addr + 8); 154 writel(0xDEADBEAF, sram_base_addr + 4); 155 dsb_sev(); 156 } 157 158 return 0; 159 } 160 161 /** 162 * rockchip_smp_prepare_sram - populate necessary sram block 163 * Starting cores execute the code residing at the start of the on-chip sram 164 * after power-on. Therefore make sure, this sram region is reserved and 165 * big enough. After this check, copy the trampoline code that directs the 166 * core to the real startup code in ram into the sram-region. 167 * @node: mmio-sram device node 168 */ 169 static int __init rockchip_smp_prepare_sram(struct device_node *node) 170 { 171 unsigned int trampoline_sz = &rockchip_secondary_trampoline_end - 172 &rockchip_secondary_trampoline; 173 struct resource res; 174 unsigned int rsize; 175 int ret; 176 177 ret = of_address_to_resource(node, 0, &res); 178 if (ret < 0) { 179 pr_err("%s: could not get address for node %s\n", 180 __func__, node->full_name); 181 return ret; 182 } 183 184 rsize = resource_size(&res); 185 if (rsize < trampoline_sz) { 186 pr_err("%s: reserved block with size 0x%x is to small for trampoline size 0x%x\n", 187 __func__, rsize, trampoline_sz); 188 return -EINVAL; 189 } 190 191 /* set the boot function for the sram code */ 192 rockchip_boot_fn = virt_to_phys(rockchip_secondary_startup); 193 194 /* copy the trampoline to sram, that runs during startup of the core */ 195 memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz); 196 flush_cache_all(); 197 outer_clean_range(0, trampoline_sz); 198 199 dsb_sev(); 200 201 return 0; 202 } 203 204 static struct regmap_config rockchip_pmu_regmap_config = { 205 .reg_bits = 32, 206 .val_bits = 32, 207 .reg_stride = 4, 208 }; 209 210 static int __init rockchip_smp_prepare_pmu(void) 211 { 212 struct device_node *node; 213 void __iomem *pmu_base; 214 215 /* 216 * This function is only called via smp_ops->smp_prepare_cpu(). 217 * That only happens if a "/cpus" device tree node exists 218 * and has an "enable-method" property that selects the SMP 219 * operations defined herein. 220 */ 221 node = of_find_node_by_path("/cpus"); 222 223 pmu = syscon_regmap_lookup_by_phandle(node, "rockchip,pmu"); 224 of_node_put(node); 225 if (!IS_ERR(pmu)) 226 return 0; 227 228 pmu = syscon_regmap_lookup_by_compatible("rockchip,rk3066-pmu"); 229 if (!IS_ERR(pmu)) 230 return 0; 231 232 /* fallback, create our own regmap for the pmu area */ 233 pmu = NULL; 234 node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu"); 235 if (!node) { 236 pr_err("%s: could not find pmu dt node\n", __func__); 237 return -ENODEV; 238 } 239 240 pmu_base = of_iomap(node, 0); 241 if (!pmu_base) { 242 pr_err("%s: could not map pmu registers\n", __func__); 243 return -ENOMEM; 244 } 245 246 pmu = regmap_init_mmio(NULL, pmu_base, &rockchip_pmu_regmap_config); 247 if (IS_ERR(pmu)) { 248 int ret = PTR_ERR(pmu); 249 250 iounmap(pmu_base); 251 pmu = NULL; 252 pr_err("%s: regmap init failed\n", __func__); 253 return ret; 254 } 255 256 return 0; 257 } 258 259 static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus) 260 { 261 struct device_node *node; 262 unsigned int i; 263 264 node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram"); 265 if (!node) { 266 pr_err("%s: could not find sram dt node\n", __func__); 267 return; 268 } 269 270 sram_base_addr = of_iomap(node, 0); 271 if (!sram_base_addr) { 272 pr_err("%s: could not map sram registers\n", __func__); 273 return; 274 } 275 276 if (rockchip_smp_prepare_pmu()) 277 return; 278 279 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) { 280 if (rockchip_smp_prepare_sram(node)) 281 return; 282 283 /* enable the SCU power domain */ 284 pmu_set_power_domain(PMU_PWRDN_SCU, true); 285 286 node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); 287 if (!node) { 288 pr_err("%s: missing scu\n", __func__); 289 return; 290 } 291 292 scu_base_addr = of_iomap(node, 0); 293 if (!scu_base_addr) { 294 pr_err("%s: could not map scu registers\n", __func__); 295 return; 296 } 297 298 /* 299 * While the number of cpus is gathered from dt, also get the 300 * number of cores from the scu to verify this value when 301 * booting the cores. 302 */ 303 ncores = scu_get_core_count(scu_base_addr); 304 pr_err("%s: ncores %d\n", __func__, ncores); 305 306 scu_enable(scu_base_addr); 307 } else { 308 unsigned int l2ctlr; 309 310 asm ("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr)); 311 ncores = ((l2ctlr >> 24) & 0x3) + 1; 312 } 313 314 /* Make sure that all cores except the first are really off */ 315 for (i = 1; i < ncores; i++) 316 pmu_set_power_domain(0 + i, false); 317 } 318 319 #ifdef CONFIG_HOTPLUG_CPU 320 static int rockchip_cpu_kill(unsigned int cpu) 321 { 322 pmu_set_power_domain(0 + cpu, false); 323 return 1; 324 } 325 326 static void rockchip_cpu_die(unsigned int cpu) 327 { 328 v7_exit_coherency_flush(louis); 329 while(1) 330 cpu_do_idle(); 331 } 332 #endif 333 334 static struct smp_operations rockchip_smp_ops __initdata = { 335 .smp_prepare_cpus = rockchip_smp_prepare_cpus, 336 .smp_boot_secondary = rockchip_boot_secondary, 337 #ifdef CONFIG_HOTPLUG_CPU 338 .cpu_kill = rockchip_cpu_kill, 339 .cpu_die = rockchip_cpu_die, 340 #endif 341 }; 342 CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops); 343