1 /* 2 * Copyright (c) 2013 MundoReader S.L. 3 * Author: Heiko Stuebner <heiko@sntech.de> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/delay.h> 17 #include <linux/init.h> 18 #include <linux/smp.h> 19 #include <linux/io.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/regmap.h> 23 #include <linux/mfd/syscon.h> 24 25 #include <linux/reset.h> 26 #include <linux/cpu.h> 27 #include <asm/cacheflush.h> 28 #include <asm/cp15.h> 29 #include <asm/smp_scu.h> 30 #include <asm/smp_plat.h> 31 #include <asm/mach/map.h> 32 33 #include "core.h" 34 35 static void __iomem *scu_base_addr; 36 static void __iomem *sram_base_addr; 37 static int ncores; 38 39 #define PMU_PWRDN_CON 0x08 40 #define PMU_PWRDN_ST 0x0c 41 42 #define PMU_PWRDN_SCU 4 43 44 static struct regmap *pmu; 45 static int has_pmu = true; 46 47 static int pmu_power_domain_is_on(int pd) 48 { 49 u32 val; 50 int ret; 51 52 ret = regmap_read(pmu, PMU_PWRDN_ST, &val); 53 if (ret < 0) 54 return ret; 55 56 return !(val & BIT(pd)); 57 } 58 59 static struct reset_control *rockchip_get_core_reset(int cpu) 60 { 61 struct device *dev = get_cpu_device(cpu); 62 struct device_node *np; 63 64 /* The cpu device is only available after the initial core bringup */ 65 if (dev) 66 np = dev->of_node; 67 else 68 np = of_get_cpu_node(cpu, NULL); 69 70 return of_reset_control_get_exclusive(np, NULL); 71 } 72 73 static int pmu_set_power_domain(int pd, bool on) 74 { 75 u32 val = (on) ? 0 : BIT(pd); 76 struct reset_control *rstc = rockchip_get_core_reset(pd); 77 int ret; 78 79 if (IS_ERR(rstc) && read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) { 80 pr_err("%s: could not get reset control for core %d\n", 81 __func__, pd); 82 return PTR_ERR(rstc); 83 } 84 85 /* 86 * We need to soft reset the cpu when we turn off the cpu power domain, 87 * or else the active processors might be stalled when the individual 88 * processor is powered down. 89 */ 90 if (!IS_ERR(rstc) && !on) 91 reset_control_assert(rstc); 92 93 if (has_pmu) { 94 ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val); 95 if (ret < 0) { 96 pr_err("%s: could not update power domain\n", 97 __func__); 98 return ret; 99 } 100 101 ret = -1; 102 while (ret != on) { 103 ret = pmu_power_domain_is_on(pd); 104 if (ret < 0) { 105 pr_err("%s: could not read power domain state\n", 106 __func__); 107 return ret; 108 } 109 } 110 } 111 112 if (!IS_ERR(rstc)) { 113 if (on) 114 reset_control_deassert(rstc); 115 reset_control_put(rstc); 116 } 117 118 return 0; 119 } 120 121 /* 122 * Handling of CPU cores 123 */ 124 125 static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle) 126 { 127 int ret; 128 129 if (!sram_base_addr || (has_pmu && !pmu)) { 130 pr_err("%s: sram or pmu missing for cpu boot\n", __func__); 131 return -ENXIO; 132 } 133 134 if (cpu >= ncores) { 135 pr_err("%s: cpu %d outside maximum number of cpus %d\n", 136 __func__, cpu, ncores); 137 return -ENXIO; 138 } 139 140 /* start the core */ 141 ret = pmu_set_power_domain(0 + cpu, true); 142 if (ret < 0) 143 return ret; 144 145 if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) { 146 /* 147 * We communicate with the bootrom to active the cpus other 148 * than cpu0, after a blob of initialize code, they will 149 * stay at wfe state, once they are actived, they will check 150 * the mailbox: 151 * sram_base_addr + 4: 0xdeadbeaf 152 * sram_base_addr + 8: start address for pc 153 * The cpu0 need to wait the other cpus other than cpu0 entering 154 * the wfe state.The wait time is affected by many aspects. 155 * (e.g: cpu frequency, bootrom frequency, sram frequency, ...) 156 */ 157 mdelay(1); /* ensure the cpus other than cpu0 to startup */ 158 159 writel(__pa_symbol(secondary_startup), sram_base_addr + 8); 160 writel(0xDEADBEAF, sram_base_addr + 4); 161 dsb_sev(); 162 } 163 164 return 0; 165 } 166 167 /** 168 * rockchip_smp_prepare_sram - populate necessary sram block 169 * Starting cores execute the code residing at the start of the on-chip sram 170 * after power-on. Therefore make sure, this sram region is reserved and 171 * big enough. After this check, copy the trampoline code that directs the 172 * core to the real startup code in ram into the sram-region. 173 * @node: mmio-sram device node 174 */ 175 static int __init rockchip_smp_prepare_sram(struct device_node *node) 176 { 177 unsigned int trampoline_sz = &rockchip_secondary_trampoline_end - 178 &rockchip_secondary_trampoline; 179 struct resource res; 180 unsigned int rsize; 181 int ret; 182 183 ret = of_address_to_resource(node, 0, &res); 184 if (ret < 0) { 185 pr_err("%s: could not get address for node %pOF\n", 186 __func__, node); 187 return ret; 188 } 189 190 rsize = resource_size(&res); 191 if (rsize < trampoline_sz) { 192 pr_err("%s: reserved block with size 0x%x is to small for trampoline size 0x%x\n", 193 __func__, rsize, trampoline_sz); 194 return -EINVAL; 195 } 196 197 /* set the boot function for the sram code */ 198 rockchip_boot_fn = __pa_symbol(secondary_startup); 199 200 /* copy the trampoline to sram, that runs during startup of the core */ 201 memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz); 202 flush_cache_all(); 203 outer_clean_range(0, trampoline_sz); 204 205 dsb_sev(); 206 207 return 0; 208 } 209 210 static const struct regmap_config rockchip_pmu_regmap_config = { 211 .name = "rockchip-pmu", 212 .reg_bits = 32, 213 .val_bits = 32, 214 .reg_stride = 4, 215 }; 216 217 static int __init rockchip_smp_prepare_pmu(void) 218 { 219 struct device_node *node; 220 void __iomem *pmu_base; 221 222 /* 223 * This function is only called via smp_ops->smp_prepare_cpu(). 224 * That only happens if a "/cpus" device tree node exists 225 * and has an "enable-method" property that selects the SMP 226 * operations defined herein. 227 */ 228 node = of_find_node_by_path("/cpus"); 229 230 pmu = syscon_regmap_lookup_by_phandle(node, "rockchip,pmu"); 231 of_node_put(node); 232 if (!IS_ERR(pmu)) 233 return 0; 234 235 pmu = syscon_regmap_lookup_by_compatible("rockchip,rk3066-pmu"); 236 if (!IS_ERR(pmu)) 237 return 0; 238 239 /* fallback, create our own regmap for the pmu area */ 240 pmu = NULL; 241 node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu"); 242 if (!node) { 243 pr_err("%s: could not find pmu dt node\n", __func__); 244 return -ENODEV; 245 } 246 247 pmu_base = of_iomap(node, 0); 248 if (!pmu_base) { 249 pr_err("%s: could not map pmu registers\n", __func__); 250 return -ENOMEM; 251 } 252 253 pmu = regmap_init_mmio(NULL, pmu_base, &rockchip_pmu_regmap_config); 254 if (IS_ERR(pmu)) { 255 int ret = PTR_ERR(pmu); 256 257 iounmap(pmu_base); 258 pmu = NULL; 259 pr_err("%s: regmap init failed\n", __func__); 260 return ret; 261 } 262 263 return 0; 264 } 265 266 static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus) 267 { 268 struct device_node *node; 269 unsigned int i; 270 271 node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram"); 272 if (!node) { 273 pr_err("%s: could not find sram dt node\n", __func__); 274 return; 275 } 276 277 sram_base_addr = of_iomap(node, 0); 278 if (!sram_base_addr) { 279 pr_err("%s: could not map sram registers\n", __func__); 280 return; 281 } 282 283 if (has_pmu && rockchip_smp_prepare_pmu()) 284 return; 285 286 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) { 287 if (rockchip_smp_prepare_sram(node)) 288 return; 289 290 /* enable the SCU power domain */ 291 pmu_set_power_domain(PMU_PWRDN_SCU, true); 292 293 node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); 294 if (!node) { 295 pr_err("%s: missing scu\n", __func__); 296 return; 297 } 298 299 scu_base_addr = of_iomap(node, 0); 300 if (!scu_base_addr) { 301 pr_err("%s: could not map scu registers\n", __func__); 302 return; 303 } 304 305 /* 306 * While the number of cpus is gathered from dt, also get the 307 * number of cores from the scu to verify this value when 308 * booting the cores. 309 */ 310 ncores = scu_get_core_count(scu_base_addr); 311 pr_err("%s: ncores %d\n", __func__, ncores); 312 313 scu_enable(scu_base_addr); 314 } else { 315 unsigned int l2ctlr; 316 317 asm ("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr)); 318 ncores = ((l2ctlr >> 24) & 0x3) + 1; 319 } 320 321 /* Make sure that all cores except the first are really off */ 322 for (i = 1; i < ncores; i++) 323 pmu_set_power_domain(0 + i, false); 324 } 325 326 static void __init rk3036_smp_prepare_cpus(unsigned int max_cpus) 327 { 328 has_pmu = false; 329 330 rockchip_smp_prepare_cpus(max_cpus); 331 } 332 333 #ifdef CONFIG_HOTPLUG_CPU 334 static int rockchip_cpu_kill(unsigned int cpu) 335 { 336 /* 337 * We need a delay here to ensure that the dying CPU can finish 338 * executing v7_coherency_exit() and reach the WFI/WFE state 339 * prior to having the power domain disabled. 340 */ 341 mdelay(1); 342 343 pmu_set_power_domain(0 + cpu, false); 344 return 1; 345 } 346 347 static void rockchip_cpu_die(unsigned int cpu) 348 { 349 v7_exit_coherency_flush(louis); 350 while (1) 351 cpu_do_idle(); 352 } 353 #endif 354 355 static const struct smp_operations rk3036_smp_ops __initconst = { 356 .smp_prepare_cpus = rk3036_smp_prepare_cpus, 357 .smp_boot_secondary = rockchip_boot_secondary, 358 #ifdef CONFIG_HOTPLUG_CPU 359 .cpu_kill = rockchip_cpu_kill, 360 .cpu_die = rockchip_cpu_die, 361 #endif 362 }; 363 364 static const struct smp_operations rockchip_smp_ops __initconst = { 365 .smp_prepare_cpus = rockchip_smp_prepare_cpus, 366 .smp_boot_secondary = rockchip_boot_secondary, 367 #ifdef CONFIG_HOTPLUG_CPU 368 .cpu_kill = rockchip_cpu_kill, 369 .cpu_die = rockchip_cpu_die, 370 #endif 371 }; 372 373 CPU_METHOD_OF_DECLARE(rk3036_smp, "rockchip,rk3036-smp", &rk3036_smp_ops); 374 CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops); 375