1/* 2 * Low-level PXA250/210 sleep/wakeUp support 3 * 4 * Initial SA1110 code: 5 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com> 6 * 7 * Adapted for PXA by Nicolas Pitre: 8 * Copyright (c) 2002 Monta Vista Software, Inc. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License. 12 */ 13 14#include <linux/linkage.h> 15#include <asm/assembler.h> 16#include <asm/hardware.h> 17 18#include <asm/arch/pxa-regs.h> 19 20#ifdef CONFIG_PXA27x // workaround for Errata 50 21#define MDREFR_KDIV 0x200a4000 // all banks 22#define CCCR_SLEEP 0x00000107 // L=7 2N=2 A=0 PPDIS=0 CPDIS=0 23#endif 24 25 .text 26 27/* 28 * pxa_cpu_suspend() 29 * 30 * Forces CPU into sleep state. 31 * 32 * r0 = value for PWRMODE M field for desired sleep state 33 */ 34 35ENTRY(pxa_cpu_suspend) 36 37#ifndef CONFIG_IWMMXT 38 mra r2, r3, acc0 39#endif 40 stmfd sp!, {r2 - r12, lr} @ save registers on stack 41 42 @ get coprocessor registers 43 mrc p14, 0, r3, c6, c0, 0 @ clock configuration, for turbo mode 44 mrc p15, 0, r4, c15, c1, 0 @ CP access reg 45 mrc p15, 0, r5, c13, c0, 0 @ PID 46 mrc p15, 0, r6, c3, c0, 0 @ domain ID 47 mrc p15, 0, r7, c2, c0, 0 @ translation table base addr 48 mrc p15, 0, r8, c1, c1, 0 @ auxiliary control reg 49 mrc p15, 0, r9, c1, c0, 0 @ control reg 50 51 bic r3, r3, #2 @ clear frequency change bit 52 53 @ store them plus current virtual stack ptr on stack 54 mov r10, sp 55 stmfd sp!, {r3 - r10} 56 57 mov r5, r0 @ save sleep mode 58 @ preserve phys address of stack 59 mov r0, sp 60 bl sleep_phys_sp 61 ldr r1, =sleep_save_sp 62 str r0, [r1] 63 64 @ clean data cache 65 bl xscale_flush_kern_cache_all 66 67 @ Put the processor to sleep 68 @ (also workaround for sighting 28071) 69 70 @ prepare value for sleep mode 71 mov r1, r5 @ sleep mode 72 73 @ prepare pointer to physical address 0 (virtual mapping in generic.c) 74 mov r2, #UNCACHED_PHYS_0 75 76 @ prepare SDRAM refresh settings 77 ldr r4, =MDREFR 78 ldr r5, [r4] 79 80 @ enable SDRAM self-refresh mode 81 orr r5, r5, #MDREFR_SLFRSH 82 83#ifdef CONFIG_PXA27x 84 @ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50) 85 ldr r6, =MDREFR_KDIV 86 orr r5, r5, r6 87#endif 88 89#ifdef CONFIG_PXA25x 90 @ Intel PXA255 Specification Update notes problems 91 @ about suspending with PXBus operating above 133MHz 92 @ (see Errata 31, GPIO output signals, ... unpredictable in sleep 93 @ 94 @ We keep the change-down close to the actual suspend on SDRAM 95 @ as possible to eliminate messing about with the refresh clock 96 @ as the system will restore with the original speed settings 97 @ 98 @ Ben Dooks, 13-Sep-2004 99 100 ldr r6, =CCCR 101 ldr r8, [r6] @ keep original value for resume 102 103 @ ensure x1 for run and turbo mode with memory clock 104 bic r7, r8, #CCCR_M_MASK | CCCR_N_MASK 105 orr r7, r7, #(1<<5) | (2<<7) 106 107 @ check that the memory frequency is within limits 108 and r14, r7, #CCCR_L_MASK 109 teq r14, #1 110 bicne r7, r7, #CCCR_L_MASK 111 orrne r7, r7, #1 @@ 99.53MHz 112 113 @ get ready for the change 114 115 @ note, turbo is not preserved over sleep so there is no 116 @ point in preserving it here. we save it on the stack with the 117 @ other CP registers instead. 118 mov r0, #0 119 mcr p14, 0, r0, c6, c0, 0 120 orr r0, r0, #2 @ initiate change bit 121#endif 122#ifdef CONFIG_PXA27x 123 @ Intel PXA270 Specification Update notes problems sleeping 124 @ with core operating above 91 MHz 125 @ (see Errata 50, ...processor does not exit from sleep...) 126 127 ldr r6, =CCCR 128 ldr r8, [r6] @ keep original value for resume 129 130 ldr r7, =CCCR_SLEEP @ prepare CCCR sleep value 131 mov r0, #0x2 @ prepare value for CLKCFG 132#endif 133 134 @ align execution to a cache line 135 b 1f 136 137 .ltorg 138 .align 5 1391: 140 141 @ All needed values are now in registers. 142 @ These last instructions should be in cache 143 144#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x) 145 @ initiate the frequency change... 146 str r7, [r6] 147 mcr p14, 0, r0, c6, c0, 0 148 149 @ restore the original cpu speed value for resume 150 str r8, [r6] 151 152 @ need 6 13-MHz cycles before changing PWRMODE 153 @ just set frequency to 91-MHz... 6*91/13 = 42 154 155 mov r0, #42 15610: subs r0, r0, #1 157 bne 10b 158#endif 159 160 @ Do not reorder... 161 @ Intel PXA270 Specification Update notes problems performing 162 @ external accesses after SDRAM is put in self-refresh mode 163 @ (see Errata 39 ...hangs when entering self-refresh mode) 164 165 @ force address lines low by reading at physical address 0 166 ldr r3, [r2] 167 168 @ put SDRAM into self-refresh 169 str r5, [r4] 170 171 @ enter sleep mode 172 mcr p14, 0, r1, c7, c0, 0 @ PWRMODE 173 17420: b 20b @ loop waiting for sleep 175 176/* 177 * cpu_pxa_resume() 178 * 179 * entry point from bootloader into kernel during resume 180 * 181 * Note: Yes, part of the following code is located into the .data section. 182 * This is to allow sleep_save_sp to be accessed with a relative load 183 * while we can't rely on any MMU translation. We could have put 184 * sleep_save_sp in the .text section as well, but some setups might 185 * insist on it to be truly read-only. 186 */ 187 188 .data 189 .align 5 190ENTRY(pxa_cpu_resume) 191 mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE @ set SVC, irqs off 192 msr cpsr_c, r0 193 194 ldr r0, sleep_save_sp @ stack phys addr 195 ldr r2, =resume_after_mmu @ its absolute virtual address 196 ldmfd r0, {r3 - r9, sp} @ CP regs + virt stack ptr 197 198 mov r1, #0 199 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 200 mcr p15, 0, r1, c7, c7, 0 @ invalidate I & D caches, BTB 201 202#ifdef CONFIG_XSCALE_CACHE_ERRATA 203 bic r9, r9, #0x0004 @ see cpu_xscale_proc_init 204#endif 205 206 mcr p14, 0, r3, c6, c0, 0 @ clock configuration, turbo mode. 207 mcr p15, 0, r4, c15, c1, 0 @ CP access reg 208 mcr p15, 0, r5, c13, c0, 0 @ PID 209 mcr p15, 0, r6, c3, c0, 0 @ domain ID 210 mcr p15, 0, r7, c2, c0, 0 @ translation table base addr 211 mcr p15, 0, r8, c1, c1, 0 @ auxiliary control reg 212 b resume_turn_on_mmu @ cache align execution 213 214 .align 5 215resume_turn_on_mmu: 216 mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, caches, etc. 217 218 @ Let us ensure we jump to resume_after_mmu only when the mcr above 219 @ actually took effect. They call it the "cpwait" operation. 220 mrc p15, 0, r1, c2, c0, 0 @ queue a dependency on CP15 221 sub pc, r2, r1, lsr #32 @ jump to virtual addr 222 nop 223 nop 224 nop 225 226sleep_save_sp: 227 .word 0 @ preserve stack phys ptr here 228 229 .text 230resume_after_mmu: 231#ifdef CONFIG_XSCALE_CACHE_ERRATA 232 bl cpu_xscale_proc_init 233#endif 234 ldmfd sp!, {r2, r3} 235#ifndef CONFIG_IWMMXT 236 mar acc0, r2, r3 237#endif 238 ldmfd sp!, {r4 - r12, pc} @ return to caller 239 240 241