1/* 2 * Low-level PXA250/210 sleep/wakeUp support 3 * 4 * Initial SA1110 code: 5 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com> 6 * 7 * Adapted for PXA by Nicolas Pitre: 8 * Copyright (c) 2002 Monta Vista Software, Inc. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License. 12 */ 13 14#include <linux/linkage.h> 15#include <asm/assembler.h> 16#include <mach/hardware.h> 17#include <mach/smemc.h> 18#include <mach/pxa2xx-regs.h> 19 20#define MDREFR_KDIV 0x200a4000 // all banks 21#define CCCR_SLEEP 0x00000107 // L=7 2N=2 A=0 PPDIS=0 CPDIS=0 22 23 .text 24 25#ifdef CONFIG_PXA3xx 26/* 27 * pxa3xx_cpu_suspend() - forces CPU into sleep state (S2D3C4) 28 * 29 * r0 = v:p offset 30 */ 31ENTRY(pxa3xx_cpu_suspend) 32 33#ifndef CONFIG_IWMMXT 34 mra r2, r3, acc0 35#endif 36 stmfd sp!, {r2 - r12, lr} @ save registers on stack 37 mov r1, r0 38 ldr r3, =pxa_cpu_resume @ resume function 39 bl cpu_suspend 40 41 mov r0, #0x06 @ S2D3C4 mode 42 mcr p14, 0, r0, c7, c0, 0 @ enter sleep 43 4420: b 20b @ waiting for sleep 45#endif /* CONFIG_PXA3xx */ 46 47#ifdef CONFIG_PXA27x 48/* 49 * pxa27x_cpu_suspend() 50 * 51 * Forces CPU into sleep state. 52 * 53 * r0 = value for PWRMODE M field for desired sleep state 54 * r1 = v:p offset 55 */ 56ENTRY(pxa27x_cpu_suspend) 57 58#ifndef CONFIG_IWMMXT 59 mra r2, r3, acc0 60#endif 61 stmfd sp!, {r2 - r12, lr} @ save registers on stack 62 mov r4, r0 @ save sleep mode 63 ldr r3, =pxa_cpu_resume @ resume function 64 bl cpu_suspend 65 66 @ Put the processor to sleep 67 @ (also workaround for sighting 28071) 68 69 @ prepare value for sleep mode 70 mov r1, r4 @ sleep mode 71 72 @ prepare pointer to physical address 0 (virtual mapping in generic.c) 73 mov r2, #UNCACHED_PHYS_0 74 75 @ prepare SDRAM refresh settings 76 ldr r4, =MDREFR 77 ldr r5, [r4] 78 79 @ enable SDRAM self-refresh mode 80 orr r5, r5, #MDREFR_SLFRSH 81 82 @ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50) 83 ldr r6, =MDREFR_KDIV 84 orr r5, r5, r6 85 86 @ Intel PXA270 Specification Update notes problems sleeping 87 @ with core operating above 91 MHz 88 @ (see Errata 50, ...processor does not exit from sleep...) 89 90 ldr r6, =CCCR 91 ldr r8, [r6] @ keep original value for resume 92 93 ldr r7, =CCCR_SLEEP @ prepare CCCR sleep value 94 mov r0, #0x2 @ prepare value for CLKCFG 95 96 @ align execution to a cache line 97 b pxa_cpu_do_suspend 98#endif 99 100#ifdef CONFIG_PXA25x 101/* 102 * pxa25x_cpu_suspend() 103 * 104 * Forces CPU into sleep state. 105 * 106 * r0 = value for PWRMODE M field for desired sleep state 107 * r1 = v:p offset 108 */ 109 110ENTRY(pxa25x_cpu_suspend) 111 stmfd sp!, {r2 - r12, lr} @ save registers on stack 112 mov r4, r0 @ save sleep mode 113 ldr r3, =pxa_cpu_resume @ resume function 114 bl cpu_suspend 115 @ prepare value for sleep mode 116 mov r1, r4 @ sleep mode 117 118 @ prepare pointer to physical address 0 (virtual mapping in generic.c) 119 mov r2, #UNCACHED_PHYS_0 120 121 @ prepare SDRAM refresh settings 122 ldr r4, =MDREFR 123 ldr r5, [r4] 124 125 @ enable SDRAM self-refresh mode 126 orr r5, r5, #MDREFR_SLFRSH 127 128 @ Intel PXA255 Specification Update notes problems 129 @ about suspending with PXBus operating above 133MHz 130 @ (see Errata 31, GPIO output signals, ... unpredictable in sleep 131 @ 132 @ We keep the change-down close to the actual suspend on SDRAM 133 @ as possible to eliminate messing about with the refresh clock 134 @ as the system will restore with the original speed settings 135 @ 136 @ Ben Dooks, 13-Sep-2004 137 138 ldr r6, =CCCR 139 ldr r8, [r6] @ keep original value for resume 140 141 @ ensure x1 for run and turbo mode with memory clock 142 bic r7, r8, #CCCR_M_MASK | CCCR_N_MASK 143 orr r7, r7, #(1<<5) | (2<<7) 144 145 @ check that the memory frequency is within limits 146 and r14, r7, #CCCR_L_MASK 147 teq r14, #1 148 bicne r7, r7, #CCCR_L_MASK 149 orrne r7, r7, #1 @@ 99.53MHz 150 151 @ get ready for the change 152 153 @ note, turbo is not preserved over sleep so there is no 154 @ point in preserving it here. we save it on the stack with the 155 @ other CP registers instead. 156 mov r0, #0 157 mcr p14, 0, r0, c6, c0, 0 158 orr r0, r0, #2 @ initiate change bit 159 b pxa_cpu_do_suspend 160#endif 161 162 .ltorg 163 .align 5 164pxa_cpu_do_suspend: 165 166 @ All needed values are now in registers. 167 @ These last instructions should be in cache 168 169 @ initiate the frequency change... 170 str r7, [r6] 171 mcr p14, 0, r0, c6, c0, 0 172 173 @ restore the original cpu speed value for resume 174 str r8, [r6] 175 176 @ need 6 13-MHz cycles before changing PWRMODE 177 @ just set frequency to 91-MHz... 6*91/13 = 42 178 179 mov r0, #42 18010: subs r0, r0, #1 181 bne 10b 182 183 @ Do not reorder... 184 @ Intel PXA270 Specification Update notes problems performing 185 @ external accesses after SDRAM is put in self-refresh mode 186 @ (see Errata 39 ...hangs when entering self-refresh mode) 187 188 @ force address lines low by reading at physical address 0 189 ldr r3, [r2] 190 191 @ put SDRAM into self-refresh 192 str r5, [r4] 193 194 @ enter sleep mode 195 mcr p14, 0, r1, c7, c0, 0 @ PWRMODE 196 19720: b 20b @ loop waiting for sleep 198 199/* 200 * pxa_cpu_resume() 201 * 202 * entry point from bootloader into kernel during resume 203 */ 204 .align 5 205pxa_cpu_resume: 206 ldmfd sp!, {r2, r3} 207#ifndef CONFIG_IWMMXT 208 mar acc0, r2, r3 209#endif 210 ldmfd sp!, {r4 - r12, pc} @ return to caller 211