1 /* 2 * linux/arch/arm/mach-pxa/pxa3xx.c 3 * 4 * code specific to pxa3xx aka Monahans 5 * 6 * Copyright (C) 2006 Marvell International Ltd. 7 * 8 * 2007-09-02: eric miao <eric.miao@marvell.com> 9 * initial version 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/kernel.h> 18 #include <linux/init.h> 19 #include <linux/pm.h> 20 #include <linux/platform_device.h> 21 #include <linux/irq.h> 22 #include <linux/io.h> 23 #include <linux/sysdev.h> 24 25 #include <asm/hardware.h> 26 #include <asm/arch/pxa3xx-regs.h> 27 #include <asm/arch/ohci.h> 28 #include <asm/arch/pm.h> 29 #include <asm/arch/dma.h> 30 #include <asm/arch/ssp.h> 31 32 #include "generic.h" 33 #include "devices.h" 34 #include "clock.h" 35 36 /* Crystal clock: 13MHz */ 37 #define BASE_CLK 13000000 38 39 /* Ring Oscillator Clock: 60MHz */ 40 #define RO_CLK 60000000 41 42 #define ACCR_D0CS (1 << 26) 43 #define ACCR_PCCE (1 << 11) 44 45 /* crystal frequency to static memory controller multiplier (SMCFS) */ 46 static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; 47 48 /* crystal frequency to HSIO bus frequency multiplier (HSS) */ 49 static unsigned char hss_mult[4] = { 8, 12, 16, 0 }; 50 51 /* 52 * Get the clock frequency as reflected by CCSR and the turbo flag. 53 * We assume these values have been applied via a fcs. 54 * If info is not 0 we also display the current settings. 55 */ 56 unsigned int pxa3xx_get_clk_frequency_khz(int info) 57 { 58 unsigned long acsr, xclkcfg; 59 unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS; 60 61 /* Read XCLKCFG register turbo bit */ 62 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); 63 t = xclkcfg & 0x1; 64 65 acsr = ACSR; 66 67 xl = acsr & 0x1f; 68 xn = (acsr >> 8) & 0x7; 69 hss = (acsr >> 14) & 0x3; 70 71 XL = xl * BASE_CLK; 72 XN = xn * XL; 73 74 ro = acsr & ACCR_D0CS; 75 76 CLK = (ro) ? RO_CLK : ((t) ? XN : XL); 77 HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK; 78 79 if (info) { 80 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n", 81 RO_CLK / 1000000, (RO_CLK % 1000000) / 10000, 82 (ro) ? "" : "in"); 83 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n", 84 XL / 1000000, (XL % 1000000) / 10000, xl); 85 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n", 86 XN / 1000000, (XN % 1000000) / 10000, xn, 87 (t) ? "" : "in"); 88 pr_info("HSIO bus clock: %d.%02dMHz\n", 89 HSS / 1000000, (HSS % 1000000) / 10000); 90 } 91 92 return CLK / 1000; 93 } 94 95 /* 96 * Return the current static memory controller clock frequency 97 * in units of 10kHz 98 */ 99 unsigned int pxa3xx_get_memclk_frequency_10khz(void) 100 { 101 unsigned long acsr; 102 unsigned int smcfs, clk = 0; 103 104 acsr = ACSR; 105 106 smcfs = (acsr >> 23) & 0x7; 107 clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK; 108 109 return (clk / 10000); 110 } 111 112 /* 113 * Return the current AC97 clock frequency. 114 */ 115 static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk) 116 { 117 unsigned long rate = 312000000; 118 unsigned long ac97_div; 119 120 ac97_div = AC97_DIV; 121 122 /* This may loose precision for some rates but won't for the 123 * standard 24.576MHz. 124 */ 125 rate /= (ac97_div >> 12) & 0x7fff; 126 rate *= (ac97_div & 0xfff); 127 128 return rate; 129 } 130 131 /* 132 * Return the current HSIO bus clock frequency 133 */ 134 static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) 135 { 136 unsigned long acsr; 137 unsigned int hss, hsio_clk; 138 139 acsr = ACSR; 140 141 hss = (acsr >> 14) & 0x3; 142 hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK; 143 144 return hsio_clk; 145 } 146 147 static void clk_pxa3xx_cken_enable(struct clk *clk) 148 { 149 unsigned long mask = 1ul << (clk->cken & 0x1f); 150 151 if (clk->cken < 32) 152 CKENA |= mask; 153 else 154 CKENB |= mask; 155 } 156 157 static void clk_pxa3xx_cken_disable(struct clk *clk) 158 { 159 unsigned long mask = 1ul << (clk->cken & 0x1f); 160 161 if (clk->cken < 32) 162 CKENA &= ~mask; 163 else 164 CKENB &= ~mask; 165 } 166 167 static const struct clkops clk_pxa3xx_cken_ops = { 168 .enable = clk_pxa3xx_cken_enable, 169 .disable = clk_pxa3xx_cken_disable, 170 }; 171 172 static const struct clkops clk_pxa3xx_hsio_ops = { 173 .enable = clk_pxa3xx_cken_enable, 174 .disable = clk_pxa3xx_cken_disable, 175 .getrate = clk_pxa3xx_hsio_getrate, 176 }; 177 178 static const struct clkops clk_pxa3xx_ac97_ops = { 179 .enable = clk_pxa3xx_cken_enable, 180 .disable = clk_pxa3xx_cken_disable, 181 .getrate = clk_pxa3xx_ac97_getrate, 182 }; 183 184 static void clk_pout_enable(struct clk *clk) 185 { 186 OSCC |= OSCC_PEN; 187 } 188 189 static void clk_pout_disable(struct clk *clk) 190 { 191 OSCC &= ~OSCC_PEN; 192 } 193 194 static const struct clkops clk_pout_ops = { 195 .enable = clk_pout_enable, 196 .disable = clk_pout_disable, 197 }; 198 199 #define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev) \ 200 { \ 201 .name = _name, \ 202 .dev = _dev, \ 203 .ops = &clk_pxa3xx_cken_ops, \ 204 .rate = _rate, \ 205 .cken = CKEN_##_cken, \ 206 .delay = _delay, \ 207 } 208 209 #define PXA3xx_CK(_name, _cken, _ops, _dev) \ 210 { \ 211 .name = _name, \ 212 .dev = _dev, \ 213 .ops = _ops, \ 214 .cken = CKEN_##_cken, \ 215 } 216 217 static struct clk pxa3xx_clks[] = { 218 { 219 .name = "CLK_POUT", 220 .ops = &clk_pout_ops, 221 .rate = 13000000, 222 .delay = 70, 223 }, 224 225 PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev), 226 PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL), 227 PXA3xx_CK("AC97CLK", AC97, &clk_pxa3xx_ac97_ops, NULL), 228 229 PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), 230 PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), 231 PXA3xx_CKEN("UARTCLK", STUART, 14857000, 1, NULL), 232 233 PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), 234 PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev), 235 PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev), 236 PXA3xx_CKEN("KBDCLK", KEYPAD, 32768, 0, &pxa27x_device_keypad.dev), 237 238 PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), 239 PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), 240 PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev), 241 PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev), 242 PXA3xx_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev), 243 PXA3xx_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev), 244 245 PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev), 246 PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev), 247 PXA3xx_CKEN("MMCCLK", MMC3, 19500000, 0, &pxa3xx_device_mci3.dev), 248 }; 249 250 #ifdef CONFIG_PM 251 252 #define ISRAM_START 0x5c000000 253 #define ISRAM_SIZE SZ_256K 254 255 static void __iomem *sram; 256 static unsigned long wakeup_src; 257 258 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 259 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 260 261 enum { SLEEP_SAVE_CKENA, 262 SLEEP_SAVE_CKENB, 263 SLEEP_SAVE_ACCR, 264 265 SLEEP_SAVE_COUNT, 266 }; 267 268 static void pxa3xx_cpu_pm_save(unsigned long *sleep_save) 269 { 270 SAVE(CKENA); 271 SAVE(CKENB); 272 SAVE(ACCR); 273 } 274 275 static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save) 276 { 277 RESTORE(ACCR); 278 RESTORE(CKENA); 279 RESTORE(CKENB); 280 } 281 282 /* 283 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic 284 * memory controller has to be reinitialised, so we place some code 285 * in the SRAM to perform this function. 286 * 287 * We disable FIQs across the standby - otherwise, we might receive a 288 * FIQ while the SDRAM is unavailable. 289 */ 290 static void pxa3xx_cpu_standby(unsigned int pwrmode) 291 { 292 extern const char pm_enter_standby_start[], pm_enter_standby_end[]; 293 void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); 294 295 memcpy_toio(sram + 0x8000, pm_enter_standby_start, 296 pm_enter_standby_end - pm_enter_standby_start); 297 298 AD2D0SR = ~0; 299 AD2D1SR = ~0; 300 AD2D0ER = wakeup_src; 301 AD2D1ER = 0; 302 ASCR = ASCR; 303 ARSR = ARSR; 304 305 local_fiq_disable(); 306 fn(pwrmode); 307 local_fiq_enable(); 308 309 AD2D0ER = 0; 310 AD2D1ER = 0; 311 } 312 313 /* 314 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with 315 * PXA3xx development kits assumes that the resuming process continues 316 * with the address stored within the first 4 bytes of SDRAM. The PSPR 317 * register is used privately by BootROM and OBM, and _must_ be set to 318 * 0x5c014000 for the moment. 319 */ 320 static void pxa3xx_cpu_pm_suspend(void) 321 { 322 volatile unsigned long *p = (volatile void *)0xc0000000; 323 unsigned long saved_data = *p; 324 325 extern void pxa3xx_cpu_suspend(void); 326 extern void pxa3xx_cpu_resume(void); 327 328 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ 329 CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); 330 CKENB |= 1 << (CKEN_HSIO2 & 0x1f); 331 332 /* clear and setup wakeup source */ 333 AD3SR = ~0; 334 AD3ER = wakeup_src; 335 ASCR = ASCR; 336 ARSR = ARSR; 337 338 PCFR |= (1u << 13); /* L1_DIS */ 339 PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ 340 341 PSPR = 0x5c014000; 342 343 /* overwrite with the resume address */ 344 *p = virt_to_phys(pxa3xx_cpu_resume); 345 346 pxa3xx_cpu_suspend(); 347 348 *p = saved_data; 349 350 AD3ER = 0; 351 } 352 353 static void pxa3xx_cpu_pm_enter(suspend_state_t state) 354 { 355 /* 356 * Don't sleep if no wakeup sources are defined 357 */ 358 if (wakeup_src == 0) { 359 printk(KERN_ERR "Not suspending: no wakeup sources\n"); 360 return; 361 } 362 363 switch (state) { 364 case PM_SUSPEND_STANDBY: 365 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); 366 break; 367 368 case PM_SUSPEND_MEM: 369 pxa3xx_cpu_pm_suspend(); 370 break; 371 } 372 } 373 374 static int pxa3xx_cpu_pm_valid(suspend_state_t state) 375 { 376 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 377 } 378 379 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { 380 .save_count = SLEEP_SAVE_COUNT, 381 .save = pxa3xx_cpu_pm_save, 382 .restore = pxa3xx_cpu_pm_restore, 383 .valid = pxa3xx_cpu_pm_valid, 384 .enter = pxa3xx_cpu_pm_enter, 385 }; 386 387 static void __init pxa3xx_init_pm(void) 388 { 389 sram = ioremap(ISRAM_START, ISRAM_SIZE); 390 if (!sram) { 391 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); 392 return; 393 } 394 395 /* 396 * Since we copy wakeup code into the SRAM, we need to ensure 397 * that it is preserved over the low power modes. Note: bit 8 398 * is undocumented in the developer manual, but must be set. 399 */ 400 AD1R |= ADXR_L2 | ADXR_R0; 401 AD2R |= ADXR_L2 | ADXR_R0; 402 AD3R |= ADXR_L2 | ADXR_R0; 403 404 /* 405 * Clear the resume enable registers. 406 */ 407 AD1D0ER = 0; 408 AD2D0ER = 0; 409 AD2D1ER = 0; 410 AD3ER = 0; 411 412 pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; 413 } 414 415 static int pxa3xx_set_wake(unsigned int irq, unsigned int on) 416 { 417 unsigned long flags, mask = 0; 418 419 switch (irq) { 420 case IRQ_SSP3: 421 mask = ADXER_MFP_WSSP3; 422 break; 423 case IRQ_MSL: 424 mask = ADXER_WMSL0; 425 break; 426 case IRQ_USBH2: 427 case IRQ_USBH1: 428 mask = ADXER_WUSBH; 429 break; 430 case IRQ_KEYPAD: 431 mask = ADXER_WKP; 432 break; 433 case IRQ_AC97: 434 mask = ADXER_MFP_WAC97; 435 break; 436 case IRQ_USIM: 437 mask = ADXER_WUSIM0; 438 break; 439 case IRQ_SSP2: 440 mask = ADXER_MFP_WSSP2; 441 break; 442 case IRQ_I2C: 443 mask = ADXER_MFP_WI2C; 444 break; 445 case IRQ_STUART: 446 mask = ADXER_MFP_WUART3; 447 break; 448 case IRQ_BTUART: 449 mask = ADXER_MFP_WUART2; 450 break; 451 case IRQ_FFUART: 452 mask = ADXER_MFP_WUART1; 453 break; 454 case IRQ_MMC: 455 mask = ADXER_MFP_WMMC1; 456 break; 457 case IRQ_SSP: 458 mask = ADXER_MFP_WSSP1; 459 break; 460 case IRQ_RTCAlrm: 461 mask = ADXER_WRTC; 462 break; 463 case IRQ_SSP4: 464 mask = ADXER_MFP_WSSP4; 465 break; 466 case IRQ_TSI: 467 mask = ADXER_WTSI; 468 break; 469 case IRQ_USIM2: 470 mask = ADXER_WUSIM1; 471 break; 472 case IRQ_MMC2: 473 mask = ADXER_MFP_WMMC2; 474 break; 475 case IRQ_NAND: 476 mask = ADXER_MFP_WFLASH; 477 break; 478 case IRQ_USB2: 479 mask = ADXER_WUSB2; 480 break; 481 case IRQ_WAKEUP0: 482 mask = ADXER_WEXTWAKE0; 483 break; 484 case IRQ_WAKEUP1: 485 mask = ADXER_WEXTWAKE1; 486 break; 487 case IRQ_MMC3: 488 mask = ADXER_MFP_GEN12; 489 break; 490 default: 491 return -EINVAL; 492 } 493 494 local_irq_save(flags); 495 if (on) 496 wakeup_src |= mask; 497 else 498 wakeup_src &= ~mask; 499 local_irq_restore(flags); 500 501 return 0; 502 } 503 #else 504 static inline void pxa3xx_init_pm(void) {} 505 #define pxa3xx_set_wake NULL 506 #endif 507 508 void __init pxa3xx_init_irq(void) 509 { 510 /* enable CP6 access */ 511 u32 value; 512 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); 513 value |= (1 << 6); 514 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); 515 516 pxa_init_irq(56, pxa3xx_set_wake); 517 pxa_init_gpio(128, NULL); 518 } 519 520 /* 521 * device registration specific to PXA3xx. 522 */ 523 524 static struct platform_device *devices[] __initdata = { 525 /* &pxa_device_udc, The UDC driver is PXA25x only */ 526 &pxa_device_ffuart, 527 &pxa_device_btuart, 528 &pxa_device_stuart, 529 &pxa_device_i2s, 530 &pxa_device_rtc, 531 &pxa27x_device_ssp1, 532 &pxa27x_device_ssp2, 533 &pxa27x_device_ssp3, 534 &pxa3xx_device_ssp4, 535 &pxa27x_device_pwm0, 536 &pxa27x_device_pwm1, 537 }; 538 539 static struct sys_device pxa3xx_sysdev[] = { 540 { 541 .cls = &pxa_irq_sysclass, 542 }, { 543 .cls = &pxa3xx_mfp_sysclass, 544 }, { 545 .cls = &pxa_gpio_sysclass, 546 }, 547 }; 548 549 static int __init pxa3xx_init(void) 550 { 551 int i, ret = 0; 552 553 if (cpu_is_pxa3xx()) { 554 /* 555 * clear RDH bit every time after reset 556 * 557 * Note: the last 3 bits DxS are write-1-to-clear so carefully 558 * preserve them here in case they will be referenced later 559 */ 560 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); 561 562 clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks)); 563 564 if ((ret = pxa_init_dma(32))) 565 return ret; 566 567 pxa3xx_init_pm(); 568 569 for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) { 570 ret = sysdev_register(&pxa3xx_sysdev[i]); 571 if (ret) 572 pr_err("failed to register sysdev[%d]\n", i); 573 } 574 575 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 576 } 577 578 return ret; 579 } 580 581 postcore_initcall(pxa3xx_init); 582