1 /* 2 * linux/arch/arm/mach-pxa/pxa3xx.c 3 * 4 * code specific to pxa3xx aka Monahans 5 * 6 * Copyright (C) 2006 Marvell International Ltd. 7 * 8 * 2007-09-02: eric miao <eric.miao@marvell.com> 9 * initial version 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/kernel.h> 18 #include <linux/init.h> 19 #include <linux/pm.h> 20 #include <linux/platform_device.h> 21 #include <linux/irq.h> 22 #include <linux/io.h> 23 #include <linux/sysdev.h> 24 25 #include <asm/hardware.h> 26 #include <asm/arch/pxa3xx-regs.h> 27 #include <asm/arch/ohci.h> 28 #include <asm/arch/pm.h> 29 #include <asm/arch/dma.h> 30 #include <asm/arch/ssp.h> 31 32 #include "generic.h" 33 #include "devices.h" 34 #include "clock.h" 35 36 /* Crystal clock: 13MHz */ 37 #define BASE_CLK 13000000 38 39 /* Ring Oscillator Clock: 60MHz */ 40 #define RO_CLK 60000000 41 42 #define ACCR_D0CS (1 << 26) 43 44 /* crystal frequency to static memory controller multiplier (SMCFS) */ 45 static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; 46 47 /* crystal frequency to HSIO bus frequency multiplier (HSS) */ 48 static unsigned char hss_mult[4] = { 8, 12, 16, 0 }; 49 50 /* 51 * Get the clock frequency as reflected by CCSR and the turbo flag. 52 * We assume these values have been applied via a fcs. 53 * If info is not 0 we also display the current settings. 54 */ 55 unsigned int pxa3xx_get_clk_frequency_khz(int info) 56 { 57 unsigned long acsr, xclkcfg; 58 unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS; 59 60 /* Read XCLKCFG register turbo bit */ 61 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); 62 t = xclkcfg & 0x1; 63 64 acsr = ACSR; 65 66 xl = acsr & 0x1f; 67 xn = (acsr >> 8) & 0x7; 68 hss = (acsr >> 14) & 0x3; 69 70 XL = xl * BASE_CLK; 71 XN = xn * XL; 72 73 ro = acsr & ACCR_D0CS; 74 75 CLK = (ro) ? RO_CLK : ((t) ? XN : XL); 76 HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK; 77 78 if (info) { 79 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n", 80 RO_CLK / 1000000, (RO_CLK % 1000000) / 10000, 81 (ro) ? "" : "in"); 82 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n", 83 XL / 1000000, (XL % 1000000) / 10000, xl); 84 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n", 85 XN / 1000000, (XN % 1000000) / 10000, xn, 86 (t) ? "" : "in"); 87 pr_info("HSIO bus clock: %d.%02dMHz\n", 88 HSS / 1000000, (HSS % 1000000) / 10000); 89 } 90 91 return CLK / 1000; 92 } 93 94 /* 95 * Return the current static memory controller clock frequency 96 * in units of 10kHz 97 */ 98 unsigned int pxa3xx_get_memclk_frequency_10khz(void) 99 { 100 unsigned long acsr; 101 unsigned int smcfs, clk = 0; 102 103 acsr = ACSR; 104 105 smcfs = (acsr >> 23) & 0x7; 106 clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK; 107 108 return (clk / 10000); 109 } 110 111 /* 112 * Return the current HSIO bus clock frequency 113 */ 114 static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) 115 { 116 unsigned long acsr; 117 unsigned int hss, hsio_clk; 118 119 acsr = ACSR; 120 121 hss = (acsr >> 14) & 0x3; 122 hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK; 123 124 return hsio_clk; 125 } 126 127 static void clk_pxa3xx_cken_enable(struct clk *clk) 128 { 129 unsigned long mask = 1ul << (clk->cken & 0x1f); 130 131 local_irq_disable(); 132 133 if (clk->cken < 32) 134 CKENA |= mask; 135 else 136 CKENB |= mask; 137 138 local_irq_enable(); 139 } 140 141 static void clk_pxa3xx_cken_disable(struct clk *clk) 142 { 143 unsigned long mask = 1ul << (clk->cken & 0x1f); 144 145 local_irq_disable(); 146 147 if (clk->cken < 32) 148 CKENA &= ~mask; 149 else 150 CKENB &= ~mask; 151 152 local_irq_enable(); 153 } 154 155 static const struct clkops clk_pxa3xx_cken_ops = { 156 .enable = clk_pxa3xx_cken_enable, 157 .disable = clk_pxa3xx_cken_disable, 158 }; 159 160 static const struct clkops clk_pxa3xx_hsio_ops = { 161 .enable = clk_pxa3xx_cken_enable, 162 .disable = clk_pxa3xx_cken_disable, 163 .getrate = clk_pxa3xx_hsio_getrate, 164 }; 165 166 #define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev) \ 167 { \ 168 .name = _name, \ 169 .dev = _dev, \ 170 .ops = &clk_pxa3xx_cken_ops, \ 171 .rate = _rate, \ 172 .cken = CKEN_##_cken, \ 173 .delay = _delay, \ 174 } 175 176 #define PXA3xx_CK(_name, _cken, _ops, _dev) \ 177 { \ 178 .name = _name, \ 179 .dev = _dev, \ 180 .ops = _ops, \ 181 .cken = CKEN_##_cken, \ 182 } 183 184 static struct clk pxa3xx_clks[] = { 185 PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev), 186 PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL), 187 188 PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), 189 PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), 190 PXA3xx_CKEN("UARTCLK", STUART, 14857000, 1, NULL), 191 192 PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), 193 PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev), 194 PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev), 195 196 PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), 197 PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), 198 PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev), 199 PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev), 200 201 PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev), 202 PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev), 203 PXA3xx_CKEN("MMCCLK", MMC3, 19500000, 0, &pxa3xx_device_mci3.dev), 204 }; 205 206 #ifdef CONFIG_PM 207 #define SLEEP_SAVE_SIZE 4 208 209 #define ISRAM_START 0x5c000000 210 #define ISRAM_SIZE SZ_256K 211 212 static void __iomem *sram; 213 static unsigned long wakeup_src; 214 215 static void pxa3xx_cpu_pm_save(unsigned long *sleep_save) 216 { 217 pr_debug("PM: CKENA=%08x CKENB=%08x\n", CKENA, CKENB); 218 219 if (CKENA & (1 << CKEN_USBH)) { 220 printk(KERN_ERR "PM: USB host clock not stopped?\n"); 221 CKENA &= ~(1 << CKEN_USBH); 222 } 223 // CKENA |= 1 << (CKEN_ISC & 31); 224 225 /* 226 * Low power modes require the HSIO2 clock to be enabled. 227 */ 228 CKENB |= 1 << (CKEN_HSIO2 & 31); 229 } 230 231 static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save) 232 { 233 CKENB &= ~(1 << (CKEN_HSIO2 & 31)); 234 } 235 236 /* 237 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic 238 * memory controller has to be reinitialised, so we place some code 239 * in the SRAM to perform this function. 240 * 241 * We disable FIQs across the standby - otherwise, we might receive a 242 * FIQ while the SDRAM is unavailable. 243 */ 244 static void pxa3xx_cpu_standby(unsigned int pwrmode) 245 { 246 extern const char pm_enter_standby_start[], pm_enter_standby_end[]; 247 void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); 248 249 memcpy_toio(sram + 0x8000, pm_enter_standby_start, 250 pm_enter_standby_end - pm_enter_standby_start); 251 252 AD2D0SR = ~0; 253 AD2D1SR = ~0; 254 AD2D0ER = wakeup_src; 255 AD2D1ER = 0; 256 ASCR = ASCR; 257 ARSR = ARSR; 258 259 local_fiq_disable(); 260 fn(pwrmode); 261 local_fiq_enable(); 262 263 AD2D0ER = 0; 264 AD2D1ER = 0; 265 266 printk("PM: AD2D0SR=%08x ASCR=%08x\n", AD2D0SR, ASCR); 267 } 268 269 static void pxa3xx_cpu_pm_enter(suspend_state_t state) 270 { 271 /* 272 * Don't sleep if no wakeup sources are defined 273 */ 274 if (wakeup_src == 0) 275 return; 276 277 switch (state) { 278 case PM_SUSPEND_STANDBY: 279 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); 280 break; 281 282 case PM_SUSPEND_MEM: 283 break; 284 } 285 } 286 287 static int pxa3xx_cpu_pm_valid(suspend_state_t state) 288 { 289 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 290 } 291 292 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { 293 .save_size = SLEEP_SAVE_SIZE, 294 .save = pxa3xx_cpu_pm_save, 295 .restore = pxa3xx_cpu_pm_restore, 296 .valid = pxa3xx_cpu_pm_valid, 297 .enter = pxa3xx_cpu_pm_enter, 298 }; 299 300 static void __init pxa3xx_init_pm(void) 301 { 302 sram = ioremap(ISRAM_START, ISRAM_SIZE); 303 if (!sram) { 304 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); 305 return; 306 } 307 308 /* 309 * Since we copy wakeup code into the SRAM, we need to ensure 310 * that it is preserved over the low power modes. Note: bit 8 311 * is undocumented in the developer manual, but must be set. 312 */ 313 AD1R |= ADXR_L2 | ADXR_R0; 314 AD2R |= ADXR_L2 | ADXR_R0; 315 AD3R |= ADXR_L2 | ADXR_R0; 316 317 /* 318 * Clear the resume enable registers. 319 */ 320 AD1D0ER = 0; 321 AD2D0ER = 0; 322 AD2D1ER = 0; 323 AD3ER = 0; 324 325 pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; 326 } 327 328 static int pxa3xx_set_wake(unsigned int irq, unsigned int on) 329 { 330 unsigned long flags, mask = 0; 331 332 switch (irq) { 333 case IRQ_SSP3: 334 mask = ADXER_MFP_WSSP3; 335 break; 336 case IRQ_MSL: 337 mask = ADXER_WMSL0; 338 break; 339 case IRQ_USBH2: 340 case IRQ_USBH1: 341 mask = ADXER_WUSBH; 342 break; 343 case IRQ_KEYPAD: 344 mask = ADXER_WKP; 345 break; 346 case IRQ_AC97: 347 mask = ADXER_MFP_WAC97; 348 break; 349 case IRQ_USIM: 350 mask = ADXER_WUSIM0; 351 break; 352 case IRQ_SSP2: 353 mask = ADXER_MFP_WSSP2; 354 break; 355 case IRQ_I2C: 356 mask = ADXER_MFP_WI2C; 357 break; 358 case IRQ_STUART: 359 mask = ADXER_MFP_WUART3; 360 break; 361 case IRQ_BTUART: 362 mask = ADXER_MFP_WUART2; 363 break; 364 case IRQ_FFUART: 365 mask = ADXER_MFP_WUART1; 366 break; 367 case IRQ_MMC: 368 mask = ADXER_MFP_WMMC1; 369 break; 370 case IRQ_SSP: 371 mask = ADXER_MFP_WSSP1; 372 break; 373 case IRQ_RTCAlrm: 374 mask = ADXER_WRTC; 375 break; 376 case IRQ_SSP4: 377 mask = ADXER_MFP_WSSP4; 378 break; 379 case IRQ_TSI: 380 mask = ADXER_WTSI; 381 break; 382 case IRQ_USIM2: 383 mask = ADXER_WUSIM1; 384 break; 385 case IRQ_MMC2: 386 mask = ADXER_MFP_WMMC2; 387 break; 388 case IRQ_NAND: 389 mask = ADXER_MFP_WFLASH; 390 break; 391 case IRQ_USB2: 392 mask = ADXER_WUSB2; 393 break; 394 case IRQ_WAKEUP0: 395 mask = ADXER_WEXTWAKE0; 396 break; 397 case IRQ_WAKEUP1: 398 mask = ADXER_WEXTWAKE1; 399 break; 400 case IRQ_MMC3: 401 mask = ADXER_MFP_GEN12; 402 break; 403 } 404 405 local_irq_save(flags); 406 if (on) 407 wakeup_src |= mask; 408 else 409 wakeup_src &= ~mask; 410 local_irq_restore(flags); 411 412 return 0; 413 } 414 415 static void pxa3xx_init_irq_pm(void) 416 { 417 pxa_init_irq_set_wake(pxa3xx_set_wake); 418 } 419 420 #else 421 static inline void pxa3xx_init_pm(void) {} 422 static inline void pxa3xx_init_irq_pm(void) {} 423 #endif 424 425 void __init pxa3xx_init_irq(void) 426 { 427 /* enable CP6 access */ 428 u32 value; 429 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); 430 value |= (1 << 6); 431 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); 432 433 pxa_init_irq_low(); 434 pxa_init_irq_high(); 435 pxa_init_irq_gpio(128); 436 pxa3xx_init_irq_pm(); 437 } 438 439 /* 440 * device registration specific to PXA3xx. 441 */ 442 443 static struct platform_device *devices[] __initdata = { 444 &pxa_device_udc, 445 &pxa_device_ffuart, 446 &pxa_device_btuart, 447 &pxa_device_stuart, 448 &pxa_device_i2s, 449 &pxa_device_rtc, 450 &pxa27x_device_ssp1, 451 &pxa27x_device_ssp2, 452 &pxa27x_device_ssp3, 453 &pxa3xx_device_ssp4, 454 }; 455 456 static struct sys_device pxa3xx_sysdev[] = { 457 { 458 .id = 0, 459 .cls = &pxa_irq_sysclass, 460 }, { 461 .id = 1, 462 .cls = &pxa_irq_sysclass, 463 }, 464 }; 465 466 static int __init pxa3xx_init(void) 467 { 468 int i, ret = 0; 469 470 if (cpu_is_pxa3xx()) { 471 clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks)); 472 473 if ((ret = pxa_init_dma(32))) 474 return ret; 475 476 pxa3xx_init_pm(); 477 478 for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) { 479 ret = sysdev_register(&pxa3xx_sysdev[i]); 480 if (ret) 481 pr_err("failed to register sysdev[%d]\n", i); 482 } 483 484 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 485 } 486 487 return ret; 488 } 489 490 subsys_initcall(pxa3xx_init); 491