1 /* 2 * linux/arch/arm/mach-pxa/pxa3xx.c 3 * 4 * code specific to pxa3xx aka Monahans 5 * 6 * Copyright (C) 2006 Marvell International Ltd. 7 * 8 * 2007-09-02: eric miao <eric.miao@marvell.com> 9 * initial version 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/kernel.h> 18 #include <linux/init.h> 19 #include <linux/pm.h> 20 #include <linux/platform_device.h> 21 #include <linux/irq.h> 22 #include <linux/io.h> 23 #include <linux/sysdev.h> 24 25 #include <asm/arch/hardware.h> 26 #include <asm/arch/pxa3xx-regs.h> 27 #include <asm/arch/ohci.h> 28 #include <asm/arch/pm.h> 29 #include <asm/arch/dma.h> 30 #include <asm/arch/ssp.h> 31 32 #include "generic.h" 33 #include "devices.h" 34 #include "clock.h" 35 36 /* Crystal clock: 13MHz */ 37 #define BASE_CLK 13000000 38 39 /* Ring Oscillator Clock: 60MHz */ 40 #define RO_CLK 60000000 41 42 #define ACCR_D0CS (1 << 26) 43 #define ACCR_PCCE (1 << 11) 44 45 /* crystal frequency to static memory controller multiplier (SMCFS) */ 46 static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; 47 48 /* crystal frequency to HSIO bus frequency multiplier (HSS) */ 49 static unsigned char hss_mult[4] = { 8, 12, 16, 0 }; 50 51 /* 52 * Get the clock frequency as reflected by CCSR and the turbo flag. 53 * We assume these values have been applied via a fcs. 54 * If info is not 0 we also display the current settings. 55 */ 56 unsigned int pxa3xx_get_clk_frequency_khz(int info) 57 { 58 unsigned long acsr, xclkcfg; 59 unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS; 60 61 /* Read XCLKCFG register turbo bit */ 62 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); 63 t = xclkcfg & 0x1; 64 65 acsr = ACSR; 66 67 xl = acsr & 0x1f; 68 xn = (acsr >> 8) & 0x7; 69 hss = (acsr >> 14) & 0x3; 70 71 XL = xl * BASE_CLK; 72 XN = xn * XL; 73 74 ro = acsr & ACCR_D0CS; 75 76 CLK = (ro) ? RO_CLK : ((t) ? XN : XL); 77 HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK; 78 79 if (info) { 80 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n", 81 RO_CLK / 1000000, (RO_CLK % 1000000) / 10000, 82 (ro) ? "" : "in"); 83 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n", 84 XL / 1000000, (XL % 1000000) / 10000, xl); 85 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n", 86 XN / 1000000, (XN % 1000000) / 10000, xn, 87 (t) ? "" : "in"); 88 pr_info("HSIO bus clock: %d.%02dMHz\n", 89 HSS / 1000000, (HSS % 1000000) / 10000); 90 } 91 92 return CLK / 1000; 93 } 94 95 /* 96 * Return the current static memory controller clock frequency 97 * in units of 10kHz 98 */ 99 unsigned int pxa3xx_get_memclk_frequency_10khz(void) 100 { 101 unsigned long acsr; 102 unsigned int smcfs, clk = 0; 103 104 acsr = ACSR; 105 106 smcfs = (acsr >> 23) & 0x7; 107 clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK; 108 109 return (clk / 10000); 110 } 111 112 /* 113 * Return the current AC97 clock frequency. 114 */ 115 static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk) 116 { 117 unsigned long rate = 312000000; 118 unsigned long ac97_div; 119 120 ac97_div = AC97_DIV; 121 122 /* This may loose precision for some rates but won't for the 123 * standard 24.576MHz. 124 */ 125 rate /= (ac97_div >> 12) & 0x7fff; 126 rate *= (ac97_div & 0xfff); 127 128 return rate; 129 } 130 131 /* 132 * Return the current HSIO bus clock frequency 133 */ 134 static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) 135 { 136 unsigned long acsr; 137 unsigned int hss, hsio_clk; 138 139 acsr = ACSR; 140 141 hss = (acsr >> 14) & 0x3; 142 hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK; 143 144 return hsio_clk; 145 } 146 147 void clk_pxa3xx_cken_enable(struct clk *clk) 148 { 149 unsigned long mask = 1ul << (clk->cken & 0x1f); 150 151 if (clk->cken < 32) 152 CKENA |= mask; 153 else 154 CKENB |= mask; 155 } 156 157 void clk_pxa3xx_cken_disable(struct clk *clk) 158 { 159 unsigned long mask = 1ul << (clk->cken & 0x1f); 160 161 if (clk->cken < 32) 162 CKENA &= ~mask; 163 else 164 CKENB &= ~mask; 165 } 166 167 const struct clkops clk_pxa3xx_cken_ops = { 168 .enable = clk_pxa3xx_cken_enable, 169 .disable = clk_pxa3xx_cken_disable, 170 }; 171 172 static const struct clkops clk_pxa3xx_hsio_ops = { 173 .enable = clk_pxa3xx_cken_enable, 174 .disable = clk_pxa3xx_cken_disable, 175 .getrate = clk_pxa3xx_hsio_getrate, 176 }; 177 178 static const struct clkops clk_pxa3xx_ac97_ops = { 179 .enable = clk_pxa3xx_cken_enable, 180 .disable = clk_pxa3xx_cken_disable, 181 .getrate = clk_pxa3xx_ac97_getrate, 182 }; 183 184 static void clk_pout_enable(struct clk *clk) 185 { 186 OSCC |= OSCC_PEN; 187 } 188 189 static void clk_pout_disable(struct clk *clk) 190 { 191 OSCC &= ~OSCC_PEN; 192 } 193 194 static const struct clkops clk_pout_ops = { 195 .enable = clk_pout_enable, 196 .disable = clk_pout_disable, 197 }; 198 199 static struct clk pxa3xx_clks[] = { 200 { 201 .name = "CLK_POUT", 202 .ops = &clk_pout_ops, 203 .rate = 13000000, 204 .delay = 70, 205 }, 206 207 PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev), 208 PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL), 209 PXA3xx_CK("AC97CLK", AC97, &clk_pxa3xx_ac97_ops, NULL), 210 211 PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), 212 PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), 213 PXA3xx_CKEN("UARTCLK", STUART, 14857000, 1, NULL), 214 215 PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), 216 PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa27x_device_udc.dev), 217 PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev), 218 PXA3xx_CKEN("KBDCLK", KEYPAD, 32768, 0, &pxa27x_device_keypad.dev), 219 220 PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), 221 PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), 222 PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev), 223 PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev), 224 PXA3xx_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev), 225 PXA3xx_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev), 226 227 PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev), 228 PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev), 229 }; 230 231 #ifdef CONFIG_PM 232 233 #define ISRAM_START 0x5c000000 234 #define ISRAM_SIZE SZ_256K 235 236 static void __iomem *sram; 237 static unsigned long wakeup_src; 238 239 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 240 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 241 242 enum { SLEEP_SAVE_CKENA, 243 SLEEP_SAVE_CKENB, 244 SLEEP_SAVE_ACCR, 245 246 SLEEP_SAVE_COUNT, 247 }; 248 249 static void pxa3xx_cpu_pm_save(unsigned long *sleep_save) 250 { 251 SAVE(CKENA); 252 SAVE(CKENB); 253 SAVE(ACCR); 254 } 255 256 static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save) 257 { 258 RESTORE(ACCR); 259 RESTORE(CKENA); 260 RESTORE(CKENB); 261 } 262 263 /* 264 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic 265 * memory controller has to be reinitialised, so we place some code 266 * in the SRAM to perform this function. 267 * 268 * We disable FIQs across the standby - otherwise, we might receive a 269 * FIQ while the SDRAM is unavailable. 270 */ 271 static void pxa3xx_cpu_standby(unsigned int pwrmode) 272 { 273 extern const char pm_enter_standby_start[], pm_enter_standby_end[]; 274 void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); 275 276 memcpy_toio(sram + 0x8000, pm_enter_standby_start, 277 pm_enter_standby_end - pm_enter_standby_start); 278 279 AD2D0SR = ~0; 280 AD2D1SR = ~0; 281 AD2D0ER = wakeup_src; 282 AD2D1ER = 0; 283 ASCR = ASCR; 284 ARSR = ARSR; 285 286 local_fiq_disable(); 287 fn(pwrmode); 288 local_fiq_enable(); 289 290 AD2D0ER = 0; 291 AD2D1ER = 0; 292 } 293 294 /* 295 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with 296 * PXA3xx development kits assumes that the resuming process continues 297 * with the address stored within the first 4 bytes of SDRAM. The PSPR 298 * register is used privately by BootROM and OBM, and _must_ be set to 299 * 0x5c014000 for the moment. 300 */ 301 static void pxa3xx_cpu_pm_suspend(void) 302 { 303 volatile unsigned long *p = (volatile void *)0xc0000000; 304 unsigned long saved_data = *p; 305 306 extern void pxa3xx_cpu_suspend(void); 307 extern void pxa3xx_cpu_resume(void); 308 309 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ 310 CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); 311 CKENB |= 1 << (CKEN_HSIO2 & 0x1f); 312 313 /* clear and setup wakeup source */ 314 AD3SR = ~0; 315 AD3ER = wakeup_src; 316 ASCR = ASCR; 317 ARSR = ARSR; 318 319 PCFR |= (1u << 13); /* L1_DIS */ 320 PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ 321 322 PSPR = 0x5c014000; 323 324 /* overwrite with the resume address */ 325 *p = virt_to_phys(pxa3xx_cpu_resume); 326 327 pxa3xx_cpu_suspend(); 328 329 *p = saved_data; 330 331 AD3ER = 0; 332 } 333 334 static void pxa3xx_cpu_pm_enter(suspend_state_t state) 335 { 336 /* 337 * Don't sleep if no wakeup sources are defined 338 */ 339 if (wakeup_src == 0) { 340 printk(KERN_ERR "Not suspending: no wakeup sources\n"); 341 return; 342 } 343 344 switch (state) { 345 case PM_SUSPEND_STANDBY: 346 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); 347 break; 348 349 case PM_SUSPEND_MEM: 350 pxa3xx_cpu_pm_suspend(); 351 break; 352 } 353 } 354 355 static int pxa3xx_cpu_pm_valid(suspend_state_t state) 356 { 357 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 358 } 359 360 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { 361 .save_count = SLEEP_SAVE_COUNT, 362 .save = pxa3xx_cpu_pm_save, 363 .restore = pxa3xx_cpu_pm_restore, 364 .valid = pxa3xx_cpu_pm_valid, 365 .enter = pxa3xx_cpu_pm_enter, 366 }; 367 368 static void __init pxa3xx_init_pm(void) 369 { 370 sram = ioremap(ISRAM_START, ISRAM_SIZE); 371 if (!sram) { 372 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); 373 return; 374 } 375 376 /* 377 * Since we copy wakeup code into the SRAM, we need to ensure 378 * that it is preserved over the low power modes. Note: bit 8 379 * is undocumented in the developer manual, but must be set. 380 */ 381 AD1R |= ADXR_L2 | ADXR_R0; 382 AD2R |= ADXR_L2 | ADXR_R0; 383 AD3R |= ADXR_L2 | ADXR_R0; 384 385 /* 386 * Clear the resume enable registers. 387 */ 388 AD1D0ER = 0; 389 AD2D0ER = 0; 390 AD2D1ER = 0; 391 AD3ER = 0; 392 393 pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; 394 } 395 396 static int pxa3xx_set_wake(unsigned int irq, unsigned int on) 397 { 398 unsigned long flags, mask = 0; 399 400 switch (irq) { 401 case IRQ_SSP3: 402 mask = ADXER_MFP_WSSP3; 403 break; 404 case IRQ_MSL: 405 mask = ADXER_WMSL0; 406 break; 407 case IRQ_USBH2: 408 case IRQ_USBH1: 409 mask = ADXER_WUSBH; 410 break; 411 case IRQ_KEYPAD: 412 mask = ADXER_WKP; 413 break; 414 case IRQ_AC97: 415 mask = ADXER_MFP_WAC97; 416 break; 417 case IRQ_USIM: 418 mask = ADXER_WUSIM0; 419 break; 420 case IRQ_SSP2: 421 mask = ADXER_MFP_WSSP2; 422 break; 423 case IRQ_I2C: 424 mask = ADXER_MFP_WI2C; 425 break; 426 case IRQ_STUART: 427 mask = ADXER_MFP_WUART3; 428 break; 429 case IRQ_BTUART: 430 mask = ADXER_MFP_WUART2; 431 break; 432 case IRQ_FFUART: 433 mask = ADXER_MFP_WUART1; 434 break; 435 case IRQ_MMC: 436 mask = ADXER_MFP_WMMC1; 437 break; 438 case IRQ_SSP: 439 mask = ADXER_MFP_WSSP1; 440 break; 441 case IRQ_RTCAlrm: 442 mask = ADXER_WRTC; 443 break; 444 case IRQ_SSP4: 445 mask = ADXER_MFP_WSSP4; 446 break; 447 case IRQ_TSI: 448 mask = ADXER_WTSI; 449 break; 450 case IRQ_USIM2: 451 mask = ADXER_WUSIM1; 452 break; 453 case IRQ_MMC2: 454 mask = ADXER_MFP_WMMC2; 455 break; 456 case IRQ_NAND: 457 mask = ADXER_MFP_WFLASH; 458 break; 459 case IRQ_USB2: 460 mask = ADXER_WUSB2; 461 break; 462 case IRQ_WAKEUP0: 463 mask = ADXER_WEXTWAKE0; 464 break; 465 case IRQ_WAKEUP1: 466 mask = ADXER_WEXTWAKE1; 467 break; 468 case IRQ_MMC3: 469 mask = ADXER_MFP_GEN12; 470 break; 471 default: 472 return -EINVAL; 473 } 474 475 local_irq_save(flags); 476 if (on) 477 wakeup_src |= mask; 478 else 479 wakeup_src &= ~mask; 480 local_irq_restore(flags); 481 482 return 0; 483 } 484 #else 485 static inline void pxa3xx_init_pm(void) {} 486 #define pxa3xx_set_wake NULL 487 #endif 488 489 void __init pxa3xx_init_irq(void) 490 { 491 /* enable CP6 access */ 492 u32 value; 493 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); 494 value |= (1 << 6); 495 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); 496 497 pxa_init_irq(56, pxa3xx_set_wake); 498 pxa_init_gpio(128, NULL); 499 } 500 501 /* 502 * device registration specific to PXA3xx. 503 */ 504 505 static struct platform_device *devices[] __initdata = { 506 /* &pxa_device_udc, The UDC driver is PXA25x only */ 507 &pxa_device_ffuart, 508 &pxa_device_btuart, 509 &pxa_device_stuart, 510 &pxa_device_i2s, 511 &pxa_device_rtc, 512 &pxa27x_device_ssp1, 513 &pxa27x_device_ssp2, 514 &pxa27x_device_ssp3, 515 &pxa3xx_device_ssp4, 516 &pxa27x_device_pwm0, 517 &pxa27x_device_pwm1, 518 }; 519 520 static struct sys_device pxa3xx_sysdev[] = { 521 { 522 .cls = &pxa_irq_sysclass, 523 }, { 524 .cls = &pxa3xx_mfp_sysclass, 525 }, { 526 .cls = &pxa_gpio_sysclass, 527 }, 528 }; 529 530 static int __init pxa3xx_init(void) 531 { 532 int i, ret = 0; 533 534 if (cpu_is_pxa3xx()) { 535 /* 536 * clear RDH bit every time after reset 537 * 538 * Note: the last 3 bits DxS are write-1-to-clear so carefully 539 * preserve them here in case they will be referenced later 540 */ 541 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); 542 543 clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks)); 544 545 if ((ret = pxa_init_dma(32))) 546 return ret; 547 548 pxa3xx_init_pm(); 549 550 for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) { 551 ret = sysdev_register(&pxa3xx_sysdev[i]); 552 if (ret) 553 pr_err("failed to register sysdev[%d]\n", i); 554 } 555 556 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 557 } 558 559 return ret; 560 } 561 562 postcore_initcall(pxa3xx_init); 563