1 /* 2 * linux/arch/arm/mach-pxa/pxa3xx.c 3 * 4 * code specific to pxa3xx aka Monahans 5 * 6 * Copyright (C) 2006 Marvell International Ltd. 7 * 8 * 2007-09-02: eric miao <eric.miao@marvell.com> 9 * initial version 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/kernel.h> 18 #include <linux/init.h> 19 #include <linux/pm.h> 20 #include <linux/platform_device.h> 21 #include <linux/irq.h> 22 #include <linux/io.h> 23 #include <linux/sysdev.h> 24 25 #include <asm/mach/map.h> 26 #include <mach/hardware.h> 27 #include <mach/gpio.h> 28 #include <mach/pxa3xx-regs.h> 29 #include <mach/reset.h> 30 #include <mach/ohci.h> 31 #include <mach/pm.h> 32 #include <mach/dma.h> 33 #include <mach/regs-intc.h> 34 #include <mach/smemc.h> 35 #include <plat/i2c.h> 36 37 #include "generic.h" 38 #include "devices.h" 39 #include "clock.h" 40 41 #define PECR_IE(n) ((1 << ((n) * 2)) << 28) 42 #define PECR_IS(n) ((1 << ((n) * 2)) << 29) 43 44 void pxa3xx_clear_reset_status(unsigned int mask) 45 { 46 /* RESET_STATUS_* has a 1:1 mapping with ARSR */ 47 ARSR = mask; 48 } 49 50 static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); 51 static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); 52 static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); 53 static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0); 54 static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5); 55 static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0); 56 static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0); 57 static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0); 58 static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0); 59 static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0); 60 static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0); 61 static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0); 62 static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0); 63 static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0); 64 static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0); 65 static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0); 66 67 static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops); 68 static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops); 69 static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops); 70 static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70); 71 72 static struct clk_lookup pxa3xx_clkregs[] = { 73 INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), 74 /* Power I2C clock is always on */ 75 INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL), 76 INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL), 77 INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"), 78 INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"), 79 INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL), 80 INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL), 81 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL), 82 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"), 83 INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL), 84 INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL), 85 INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL), 86 INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL), 87 INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL), 88 INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL), 89 INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL), 90 INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL), 91 INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL), 92 INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL), 93 INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL), 94 INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL), 95 INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL), 96 }; 97 98 #ifdef CONFIG_PM 99 100 #define ISRAM_START 0x5c000000 101 #define ISRAM_SIZE SZ_256K 102 103 static void __iomem *sram; 104 static unsigned long wakeup_src; 105 106 /* 107 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic 108 * memory controller has to be reinitialised, so we place some code 109 * in the SRAM to perform this function. 110 * 111 * We disable FIQs across the standby - otherwise, we might receive a 112 * FIQ while the SDRAM is unavailable. 113 */ 114 static void pxa3xx_cpu_standby(unsigned int pwrmode) 115 { 116 extern const char pm_enter_standby_start[], pm_enter_standby_end[]; 117 void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); 118 119 memcpy_toio(sram + 0x8000, pm_enter_standby_start, 120 pm_enter_standby_end - pm_enter_standby_start); 121 122 AD2D0SR = ~0; 123 AD2D1SR = ~0; 124 AD2D0ER = wakeup_src; 125 AD2D1ER = 0; 126 ASCR = ASCR; 127 ARSR = ARSR; 128 129 local_fiq_disable(); 130 fn(pwrmode); 131 local_fiq_enable(); 132 133 AD2D0ER = 0; 134 AD2D1ER = 0; 135 } 136 137 /* 138 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with 139 * PXA3xx development kits assumes that the resuming process continues 140 * with the address stored within the first 4 bytes of SDRAM. The PSPR 141 * register is used privately by BootROM and OBM, and _must_ be set to 142 * 0x5c014000 for the moment. 143 */ 144 static void pxa3xx_cpu_pm_suspend(void) 145 { 146 volatile unsigned long *p = (volatile void *)0xc0000000; 147 unsigned long saved_data = *p; 148 149 extern void pxa3xx_cpu_suspend(void); 150 extern void pxa3xx_cpu_resume(void); 151 152 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ 153 CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); 154 CKENB |= 1 << (CKEN_HSIO2 & 0x1f); 155 156 /* clear and setup wakeup source */ 157 AD3SR = ~0; 158 AD3ER = wakeup_src; 159 ASCR = ASCR; 160 ARSR = ARSR; 161 162 PCFR |= (1u << 13); /* L1_DIS */ 163 PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ 164 165 PSPR = 0x5c014000; 166 167 /* overwrite with the resume address */ 168 *p = virt_to_phys(pxa3xx_cpu_resume); 169 170 pxa3xx_cpu_suspend(); 171 172 *p = saved_data; 173 174 AD3ER = 0; 175 } 176 177 static void pxa3xx_cpu_pm_enter(suspend_state_t state) 178 { 179 /* 180 * Don't sleep if no wakeup sources are defined 181 */ 182 if (wakeup_src == 0) { 183 printk(KERN_ERR "Not suspending: no wakeup sources\n"); 184 return; 185 } 186 187 switch (state) { 188 case PM_SUSPEND_STANDBY: 189 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); 190 break; 191 192 case PM_SUSPEND_MEM: 193 pxa3xx_cpu_pm_suspend(); 194 break; 195 } 196 } 197 198 static int pxa3xx_cpu_pm_valid(suspend_state_t state) 199 { 200 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 201 } 202 203 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { 204 .valid = pxa3xx_cpu_pm_valid, 205 .enter = pxa3xx_cpu_pm_enter, 206 }; 207 208 static void __init pxa3xx_init_pm(void) 209 { 210 sram = ioremap(ISRAM_START, ISRAM_SIZE); 211 if (!sram) { 212 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); 213 return; 214 } 215 216 /* 217 * Since we copy wakeup code into the SRAM, we need to ensure 218 * that it is preserved over the low power modes. Note: bit 8 219 * is undocumented in the developer manual, but must be set. 220 */ 221 AD1R |= ADXR_L2 | ADXR_R0; 222 AD2R |= ADXR_L2 | ADXR_R0; 223 AD3R |= ADXR_L2 | ADXR_R0; 224 225 /* 226 * Clear the resume enable registers. 227 */ 228 AD1D0ER = 0; 229 AD2D0ER = 0; 230 AD2D1ER = 0; 231 AD3ER = 0; 232 233 pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; 234 } 235 236 static int pxa3xx_set_wake(unsigned int irq, unsigned int on) 237 { 238 unsigned long flags, mask = 0; 239 240 switch (irq) { 241 case IRQ_SSP3: 242 mask = ADXER_MFP_WSSP3; 243 break; 244 case IRQ_MSL: 245 mask = ADXER_WMSL0; 246 break; 247 case IRQ_USBH2: 248 case IRQ_USBH1: 249 mask = ADXER_WUSBH; 250 break; 251 case IRQ_KEYPAD: 252 mask = ADXER_WKP; 253 break; 254 case IRQ_AC97: 255 mask = ADXER_MFP_WAC97; 256 break; 257 case IRQ_USIM: 258 mask = ADXER_WUSIM0; 259 break; 260 case IRQ_SSP2: 261 mask = ADXER_MFP_WSSP2; 262 break; 263 case IRQ_I2C: 264 mask = ADXER_MFP_WI2C; 265 break; 266 case IRQ_STUART: 267 mask = ADXER_MFP_WUART3; 268 break; 269 case IRQ_BTUART: 270 mask = ADXER_MFP_WUART2; 271 break; 272 case IRQ_FFUART: 273 mask = ADXER_MFP_WUART1; 274 break; 275 case IRQ_MMC: 276 mask = ADXER_MFP_WMMC1; 277 break; 278 case IRQ_SSP: 279 mask = ADXER_MFP_WSSP1; 280 break; 281 case IRQ_RTCAlrm: 282 mask = ADXER_WRTC; 283 break; 284 case IRQ_SSP4: 285 mask = ADXER_MFP_WSSP4; 286 break; 287 case IRQ_TSI: 288 mask = ADXER_WTSI; 289 break; 290 case IRQ_USIM2: 291 mask = ADXER_WUSIM1; 292 break; 293 case IRQ_MMC2: 294 mask = ADXER_MFP_WMMC2; 295 break; 296 case IRQ_NAND: 297 mask = ADXER_MFP_WFLASH; 298 break; 299 case IRQ_USB2: 300 mask = ADXER_WUSB2; 301 break; 302 case IRQ_WAKEUP0: 303 mask = ADXER_WEXTWAKE0; 304 break; 305 case IRQ_WAKEUP1: 306 mask = ADXER_WEXTWAKE1; 307 break; 308 case IRQ_MMC3: 309 mask = ADXER_MFP_GEN12; 310 break; 311 default: 312 return -EINVAL; 313 } 314 315 local_irq_save(flags); 316 if (on) 317 wakeup_src |= mask; 318 else 319 wakeup_src &= ~mask; 320 local_irq_restore(flags); 321 322 return 0; 323 } 324 #else 325 static inline void pxa3xx_init_pm(void) {} 326 #define pxa3xx_set_wake NULL 327 #endif 328 329 static void pxa_ack_ext_wakeup(unsigned int irq) 330 { 331 PECR |= PECR_IS(irq - IRQ_WAKEUP0); 332 } 333 334 static void pxa_mask_ext_wakeup(unsigned int irq) 335 { 336 ICMR2 &= ~(1 << ((irq - PXA_IRQ(0)) & 0x1f)); 337 PECR &= ~PECR_IE(irq - IRQ_WAKEUP0); 338 } 339 340 static void pxa_unmask_ext_wakeup(unsigned int irq) 341 { 342 ICMR2 |= 1 << ((irq - PXA_IRQ(0)) & 0x1f); 343 PECR |= PECR_IE(irq - IRQ_WAKEUP0); 344 } 345 346 static int pxa_set_ext_wakeup_type(unsigned int irq, unsigned int flow_type) 347 { 348 if (flow_type & IRQ_TYPE_EDGE_RISING) 349 PWER |= 1 << (irq - IRQ_WAKEUP0); 350 351 if (flow_type & IRQ_TYPE_EDGE_FALLING) 352 PWER |= 1 << (irq - IRQ_WAKEUP0 + 2); 353 354 return 0; 355 } 356 357 static struct irq_chip pxa_ext_wakeup_chip = { 358 .name = "WAKEUP", 359 .ack = pxa_ack_ext_wakeup, 360 .mask = pxa_mask_ext_wakeup, 361 .unmask = pxa_unmask_ext_wakeup, 362 .set_type = pxa_set_ext_wakeup_type, 363 }; 364 365 static void __init pxa_init_ext_wakeup_irq(set_wake_t fn) 366 { 367 int irq; 368 369 for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { 370 set_irq_chip(irq, &pxa_ext_wakeup_chip); 371 set_irq_handler(irq, handle_edge_irq); 372 set_irq_flags(irq, IRQF_VALID); 373 } 374 375 pxa_ext_wakeup_chip.set_wake = fn; 376 } 377 378 void __init pxa3xx_init_irq(void) 379 { 380 /* enable CP6 access */ 381 u32 value; 382 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); 383 value |= (1 << 6); 384 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); 385 386 pxa_init_irq(56, pxa3xx_set_wake); 387 pxa_init_ext_wakeup_irq(pxa3xx_set_wake); 388 pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL); 389 } 390 391 static struct map_desc pxa3xx_io_desc[] __initdata = { 392 { /* Mem Ctl */ 393 .virtual = SMEMC_VIRT, 394 .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE), 395 .length = 0x00200000, 396 .type = MT_DEVICE 397 } 398 }; 399 400 void __init pxa3xx_map_io(void) 401 { 402 pxa_map_io(); 403 iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc)); 404 pxa3xx_get_clk_frequency_khz(1); 405 } 406 407 /* 408 * device registration specific to PXA3xx. 409 */ 410 411 void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) 412 { 413 pxa_register_device(&pxa3xx_device_i2c_power, info); 414 } 415 416 static struct platform_device *devices[] __initdata = { 417 &pxa27x_device_udc, 418 &pxa_device_pmu, 419 &pxa_device_i2s, 420 &pxa_device_asoc_ssp1, 421 &pxa_device_asoc_ssp2, 422 &pxa_device_asoc_ssp3, 423 &pxa_device_asoc_ssp4, 424 &pxa_device_asoc_platform, 425 &sa1100_device_rtc, 426 &pxa_device_rtc, 427 &pxa27x_device_ssp1, 428 &pxa27x_device_ssp2, 429 &pxa27x_device_ssp3, 430 &pxa3xx_device_ssp4, 431 &pxa27x_device_pwm0, 432 &pxa27x_device_pwm1, 433 }; 434 435 static struct sys_device pxa3xx_sysdev[] = { 436 { 437 .cls = &pxa_irq_sysclass, 438 }, { 439 .cls = &pxa3xx_mfp_sysclass, 440 }, { 441 .cls = &pxa_gpio_sysclass, 442 }, { 443 .cls = &pxa3xx_clock_sysclass, 444 } 445 }; 446 447 static int __init pxa3xx_init(void) 448 { 449 int i, ret = 0; 450 451 if (cpu_is_pxa3xx()) { 452 453 reset_status = ARSR; 454 455 /* 456 * clear RDH bit every time after reset 457 * 458 * Note: the last 3 bits DxS are write-1-to-clear so carefully 459 * preserve them here in case they will be referenced later 460 */ 461 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); 462 463 clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs)); 464 465 if ((ret = pxa_init_dma(IRQ_DMA, 32))) 466 return ret; 467 468 pxa3xx_init_pm(); 469 470 for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) { 471 ret = sysdev_register(&pxa3xx_sysdev[i]); 472 if (ret) 473 pr_err("failed to register sysdev[%d]\n", i); 474 } 475 476 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 477 } 478 479 return ret; 480 } 481 482 postcore_initcall(pxa3xx_init); 483