xref: /openbmc/linux/arch/arm/mach-pxa/pxa3xx.c (revision a9a54cae) 
1 /*
2  * linux/arch/arm/mach-pxa/pxa3xx.c
3  *
4  * code specific to pxa3xx aka Monahans
5  *
6  * Copyright (C) 2006 Marvell International Ltd.
7  *
8  * 2007-09-02: eric miao <eric.miao@marvell.com>
9  *             initial version
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License version 2 as
13  * published by the Free Software Foundation.
14  */
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/gpio-pxa.h>
19 #include <linux/pm.h>
20 #include <linux/platform_device.h>
21 #include <linux/irq.h>
22 #include <linux/io.h>
23 #include <linux/of.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/i2c/pxa-i2c.h>
26 
27 #include <asm/mach/map.h>
28 #include <asm/suspend.h>
29 #include <mach/hardware.h>
30 #include <mach/pxa3xx-regs.h>
31 #include <mach/reset.h>
32 #include <linux/platform_data/usb-ohci-pxa27x.h>
33 #include "pm.h"
34 #include <mach/dma.h>
35 #include <mach/smemc.h>
36 #include <mach/irqs.h>
37 
38 #include "generic.h"
39 #include "devices.h"
40 
41 #define PECR_IE(n)	((1 << ((n) * 2)) << 28)
42 #define PECR_IS(n)	((1 << ((n) * 2)) << 29)
43 
44 extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));
45 
46 /*
47  * NAND NFC: DFI bus arbitration subset
48  */
49 #define NDCR			(*(volatile u32 __iomem*)(NAND_VIRT + 0))
50 #define NDCR_ND_ARB_EN		(1 << 12)
51 #define NDCR_ND_ARB_CNTL	(1 << 19)
52 
53 #ifdef CONFIG_PM
54 
55 #define ISRAM_START	0x5c000000
56 #define ISRAM_SIZE	SZ_256K
57 
58 static void __iomem *sram;
59 static unsigned long wakeup_src;
60 
61 /*
62  * Enter a standby mode (S0D1C2 or S0D2C2).  Upon wakeup, the dynamic
63  * memory controller has to be reinitialised, so we place some code
64  * in the SRAM to perform this function.
65  *
66  * We disable FIQs across the standby - otherwise, we might receive a
67  * FIQ while the SDRAM is unavailable.
68  */
69 static void pxa3xx_cpu_standby(unsigned int pwrmode)
70 {
71 	void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
72 
73 	memcpy_toio(sram + 0x8000, pm_enter_standby_start,
74 		    pm_enter_standby_end - pm_enter_standby_start);
75 
76 	AD2D0SR = ~0;
77 	AD2D1SR = ~0;
78 	AD2D0ER = wakeup_src;
79 	AD2D1ER = 0;
80 	ASCR = ASCR;
81 	ARSR = ARSR;
82 
83 	local_fiq_disable();
84 	fn(pwrmode);
85 	local_fiq_enable();
86 
87 	AD2D0ER = 0;
88 	AD2D1ER = 0;
89 }
90 
91 /*
92  * NOTE:  currently, the OBM (OEM Boot Module) binary comes along with
93  * PXA3xx development kits assumes that the resuming process continues
94  * with the address stored within the first 4 bytes of SDRAM. The PSPR
95  * register is used privately by BootROM and OBM, and _must_ be set to
96  * 0x5c014000 for the moment.
97  */
98 static void pxa3xx_cpu_pm_suspend(void)
99 {
100 	volatile unsigned long *p = (volatile void *)0xc0000000;
101 	unsigned long saved_data = *p;
102 #ifndef CONFIG_IWMMXT
103 	u64 acc0;
104 
105 	asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
106 #endif
107 
108 	/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
109 	CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
110 	CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
111 
112 	/* clear and setup wakeup source */
113 	AD3SR = ~0;
114 	AD3ER = wakeup_src;
115 	ASCR = ASCR;
116 	ARSR = ARSR;
117 
118 	PCFR |= (1u << 13);			/* L1_DIS */
119 	PCFR &= ~((1u << 12) | (1u << 1));	/* L0_EN | SL_ROD */
120 
121 	PSPR = 0x5c014000;
122 
123 	/* overwrite with the resume address */
124 	*p = virt_to_phys(cpu_resume);
125 
126 	cpu_suspend(0, pxa3xx_finish_suspend);
127 
128 	*p = saved_data;
129 
130 	AD3ER = 0;
131 
132 #ifndef CONFIG_IWMMXT
133 	asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
134 #endif
135 }
136 
137 static void pxa3xx_cpu_pm_enter(suspend_state_t state)
138 {
139 	/*
140 	 * Don't sleep if no wakeup sources are defined
141 	 */
142 	if (wakeup_src == 0) {
143 		printk(KERN_ERR "Not suspending: no wakeup sources\n");
144 		return;
145 	}
146 
147 	switch (state) {
148 	case PM_SUSPEND_STANDBY:
149 		pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
150 		break;
151 
152 	case PM_SUSPEND_MEM:
153 		pxa3xx_cpu_pm_suspend();
154 		break;
155 	}
156 }
157 
158 static int pxa3xx_cpu_pm_valid(suspend_state_t state)
159 {
160 	return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
161 }
162 
163 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
164 	.valid		= pxa3xx_cpu_pm_valid,
165 	.enter		= pxa3xx_cpu_pm_enter,
166 };
167 
168 static void __init pxa3xx_init_pm(void)
169 {
170 	sram = ioremap(ISRAM_START, ISRAM_SIZE);
171 	if (!sram) {
172 		printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
173 		return;
174 	}
175 
176 	/*
177 	 * Since we copy wakeup code into the SRAM, we need to ensure
178 	 * that it is preserved over the low power modes.  Note: bit 8
179 	 * is undocumented in the developer manual, but must be set.
180 	 */
181 	AD1R |= ADXR_L2 | ADXR_R0;
182 	AD2R |= ADXR_L2 | ADXR_R0;
183 	AD3R |= ADXR_L2 | ADXR_R0;
184 
185 	/*
186 	 * Clear the resume enable registers.
187 	 */
188 	AD1D0ER = 0;
189 	AD2D0ER = 0;
190 	AD2D1ER = 0;
191 	AD3ER = 0;
192 
193 	pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
194 }
195 
196 static int pxa3xx_set_wake(struct irq_data *d, unsigned int on)
197 {
198 	unsigned long flags, mask = 0;
199 
200 	switch (d->irq) {
201 	case IRQ_SSP3:
202 		mask = ADXER_MFP_WSSP3;
203 		break;
204 	case IRQ_MSL:
205 		mask = ADXER_WMSL0;
206 		break;
207 	case IRQ_USBH2:
208 	case IRQ_USBH1:
209 		mask = ADXER_WUSBH;
210 		break;
211 	case IRQ_KEYPAD:
212 		mask = ADXER_WKP;
213 		break;
214 	case IRQ_AC97:
215 		mask = ADXER_MFP_WAC97;
216 		break;
217 	case IRQ_USIM:
218 		mask = ADXER_WUSIM0;
219 		break;
220 	case IRQ_SSP2:
221 		mask = ADXER_MFP_WSSP2;
222 		break;
223 	case IRQ_I2C:
224 		mask = ADXER_MFP_WI2C;
225 		break;
226 	case IRQ_STUART:
227 		mask = ADXER_MFP_WUART3;
228 		break;
229 	case IRQ_BTUART:
230 		mask = ADXER_MFP_WUART2;
231 		break;
232 	case IRQ_FFUART:
233 		mask = ADXER_MFP_WUART1;
234 		break;
235 	case IRQ_MMC:
236 		mask = ADXER_MFP_WMMC1;
237 		break;
238 	case IRQ_SSP:
239 		mask = ADXER_MFP_WSSP1;
240 		break;
241 	case IRQ_RTCAlrm:
242 		mask = ADXER_WRTC;
243 		break;
244 	case IRQ_SSP4:
245 		mask = ADXER_MFP_WSSP4;
246 		break;
247 	case IRQ_TSI:
248 		mask = ADXER_WTSI;
249 		break;
250 	case IRQ_USIM2:
251 		mask = ADXER_WUSIM1;
252 		break;
253 	case IRQ_MMC2:
254 		mask = ADXER_MFP_WMMC2;
255 		break;
256 	case IRQ_NAND:
257 		mask = ADXER_MFP_WFLASH;
258 		break;
259 	case IRQ_USB2:
260 		mask = ADXER_WUSB2;
261 		break;
262 	case IRQ_WAKEUP0:
263 		mask = ADXER_WEXTWAKE0;
264 		break;
265 	case IRQ_WAKEUP1:
266 		mask = ADXER_WEXTWAKE1;
267 		break;
268 	case IRQ_MMC3:
269 		mask = ADXER_MFP_GEN12;
270 		break;
271 	default:
272 		return -EINVAL;
273 	}
274 
275 	local_irq_save(flags);
276 	if (on)
277 		wakeup_src |= mask;
278 	else
279 		wakeup_src &= ~mask;
280 	local_irq_restore(flags);
281 
282 	return 0;
283 }
284 #else
285 static inline void pxa3xx_init_pm(void) {}
286 #define pxa3xx_set_wake	NULL
287 #endif
288 
289 static void pxa_ack_ext_wakeup(struct irq_data *d)
290 {
291 	PECR |= PECR_IS(d->irq - IRQ_WAKEUP0);
292 }
293 
294 static void pxa_mask_ext_wakeup(struct irq_data *d)
295 {
296 	pxa_mask_irq(d);
297 	PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);
298 }
299 
300 static void pxa_unmask_ext_wakeup(struct irq_data *d)
301 {
302 	pxa_unmask_irq(d);
303 	PECR |= PECR_IE(d->irq - IRQ_WAKEUP0);
304 }
305 
306 static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type)
307 {
308 	if (flow_type & IRQ_TYPE_EDGE_RISING)
309 		PWER |= 1 << (d->irq - IRQ_WAKEUP0);
310 
311 	if (flow_type & IRQ_TYPE_EDGE_FALLING)
312 		PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2);
313 
314 	return 0;
315 }
316 
317 static struct irq_chip pxa_ext_wakeup_chip = {
318 	.name		= "WAKEUP",
319 	.irq_ack	= pxa_ack_ext_wakeup,
320 	.irq_mask	= pxa_mask_ext_wakeup,
321 	.irq_unmask	= pxa_unmask_ext_wakeup,
322 	.irq_set_type	= pxa_set_ext_wakeup_type,
323 };
324 
325 static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *,
326 					   unsigned int))
327 {
328 	int irq;
329 
330 	for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
331 		irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
332 					 handle_edge_irq);
333 		irq_clear_status_flags(irq, IRQ_NOREQUEST);
334 	}
335 
336 	pxa_ext_wakeup_chip.irq_set_wake = fn;
337 }
338 
339 static void __init __pxa3xx_init_irq(void)
340 {
341 	/* enable CP6 access */
342 	u32 value;
343 	__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
344 	value |= (1 << 6);
345 	__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
346 
347 	pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
348 }
349 
350 void __init pxa3xx_init_irq(void)
351 {
352 	__pxa3xx_init_irq();
353 	pxa_init_irq(56, pxa3xx_set_wake);
354 }
355 
356 #ifdef CONFIG_OF
357 void __init pxa3xx_dt_init_irq(void)
358 {
359 	__pxa3xx_init_irq();
360 	pxa_dt_irq_init(pxa3xx_set_wake);
361 }
362 #endif	/* CONFIG_OF */
363 
364 static struct map_desc pxa3xx_io_desc[] __initdata = {
365 	{	/* Mem Ctl */
366 		.virtual	= (unsigned long)SMEMC_VIRT,
367 		.pfn		= __phys_to_pfn(PXA3XX_SMEMC_BASE),
368 		.length		= SMEMC_SIZE,
369 		.type		= MT_DEVICE
370 	}, {
371 		.virtual	= (unsigned long)NAND_VIRT,
372 		.pfn		= __phys_to_pfn(NAND_PHYS),
373 		.length		= NAND_SIZE,
374 		.type		= MT_DEVICE
375 	},
376 };
377 
378 void __init pxa3xx_map_io(void)
379 {
380 	pxa_map_io();
381 	iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
382 	pxa3xx_get_clk_frequency_khz(1);
383 }
384 
385 /*
386  * device registration specific to PXA3xx.
387  */
388 
389 void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
390 {
391 	pxa_register_device(&pxa3xx_device_i2c_power, info);
392 }
393 
394 static struct pxa_gpio_platform_data pxa3xx_gpio_pdata = {
395 	.irq_base	= PXA_GPIO_TO_IRQ(0),
396 };
397 
398 static struct platform_device *devices[] __initdata = {
399 	&pxa27x_device_udc,
400 	&pxa_device_pmu,
401 	&pxa_device_i2s,
402 	&pxa_device_asoc_ssp1,
403 	&pxa_device_asoc_ssp2,
404 	&pxa_device_asoc_ssp3,
405 	&pxa_device_asoc_ssp4,
406 	&pxa_device_asoc_platform,
407 	&pxa_device_rtc,
408 	&pxa3xx_device_ssp1,
409 	&pxa3xx_device_ssp2,
410 	&pxa3xx_device_ssp3,
411 	&pxa3xx_device_ssp4,
412 	&pxa27x_device_pwm0,
413 	&pxa27x_device_pwm1,
414 };
415 
416 static int __init pxa3xx_init(void)
417 {
418 	int ret = 0;
419 
420 	if (cpu_is_pxa3xx()) {
421 
422 		reset_status = ARSR;
423 
424 		/*
425 		 * clear RDH bit every time after reset
426 		 *
427 		 * Note: the last 3 bits DxS are write-1-to-clear so carefully
428 		 * preserve them here in case they will be referenced later
429 		 */
430 		ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
431 
432 		/*
433 		 * Disable DFI bus arbitration, to prevent a system bus lock if
434 		 * somebody disables the NAND clock (unused clock) while this
435 		 * bit remains set.
436 		 */
437 		NDCR = (NDCR & ~NDCR_ND_ARB_EN) | NDCR_ND_ARB_CNTL;
438 
439 		if ((ret = pxa_init_dma(IRQ_DMA, 32)))
440 			return ret;
441 
442 		pxa3xx_init_pm();
443 
444 		register_syscore_ops(&pxa_irq_syscore_ops);
445 		register_syscore_ops(&pxa3xx_mfp_syscore_ops);
446 
447 		if (of_have_populated_dt())
448 			return 0;
449 
450 		pxa2xx_set_dmac_info(32);
451 		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
452 		if (ret)
453 			return ret;
454 		if (cpu_is_pxa300() || cpu_is_pxa310() || cpu_is_pxa320()) {
455 			platform_device_add_data(&pxa3xx_device_gpio,
456 						 &pxa3xx_gpio_pdata,
457 						 sizeof(pxa3xx_gpio_pdata));
458 			ret = platform_device_register(&pxa3xx_device_gpio);
459 		}
460 	}
461 
462 	return ret;
463 }
464 
465 postcore_initcall(pxa3xx_init);
466