1 /* 2 * linux/arch/arm/mach-pxa/pxa3xx.c 3 * 4 * code specific to pxa3xx aka Monahans 5 * 6 * Copyright (C) 2006 Marvell International Ltd. 7 * 8 * 2007-09-02: eric miao <eric.miao@marvell.com> 9 * initial version 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/kernel.h> 18 #include <linux/init.h> 19 #include <linux/pm.h> 20 #include <linux/platform_device.h> 21 #include <linux/irq.h> 22 #include <linux/io.h> 23 #include <linux/sysdev.h> 24 25 #include <mach/hardware.h> 26 #include <mach/pxa3xx-regs.h> 27 #include <mach/reset.h> 28 #include <mach/ohci.h> 29 #include <mach/pm.h> 30 #include <mach/dma.h> 31 #include <mach/ssp.h> 32 33 #include "generic.h" 34 #include "devices.h" 35 #include "clock.h" 36 37 /* Crystal clock: 13MHz */ 38 #define BASE_CLK 13000000 39 40 /* Ring Oscillator Clock: 60MHz */ 41 #define RO_CLK 60000000 42 43 #define ACCR_D0CS (1 << 26) 44 #define ACCR_PCCE (1 << 11) 45 46 /* crystal frequency to static memory controller multiplier (SMCFS) */ 47 static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; 48 49 /* crystal frequency to HSIO bus frequency multiplier (HSS) */ 50 static unsigned char hss_mult[4] = { 8, 12, 16, 0 }; 51 52 /* 53 * Get the clock frequency as reflected by CCSR and the turbo flag. 54 * We assume these values have been applied via a fcs. 55 * If info is not 0 we also display the current settings. 56 */ 57 unsigned int pxa3xx_get_clk_frequency_khz(int info) 58 { 59 unsigned long acsr, xclkcfg; 60 unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS; 61 62 /* Read XCLKCFG register turbo bit */ 63 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); 64 t = xclkcfg & 0x1; 65 66 acsr = ACSR; 67 68 xl = acsr & 0x1f; 69 xn = (acsr >> 8) & 0x7; 70 hss = (acsr >> 14) & 0x3; 71 72 XL = xl * BASE_CLK; 73 XN = xn * XL; 74 75 ro = acsr & ACCR_D0CS; 76 77 CLK = (ro) ? RO_CLK : ((t) ? XN : XL); 78 HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK; 79 80 if (info) { 81 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n", 82 RO_CLK / 1000000, (RO_CLK % 1000000) / 10000, 83 (ro) ? "" : "in"); 84 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n", 85 XL / 1000000, (XL % 1000000) / 10000, xl); 86 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n", 87 XN / 1000000, (XN % 1000000) / 10000, xn, 88 (t) ? "" : "in"); 89 pr_info("HSIO bus clock: %d.%02dMHz\n", 90 HSS / 1000000, (HSS % 1000000) / 10000); 91 } 92 93 return CLK / 1000; 94 } 95 96 /* 97 * Return the current static memory controller clock frequency 98 * in units of 10kHz 99 */ 100 unsigned int pxa3xx_get_memclk_frequency_10khz(void) 101 { 102 unsigned long acsr; 103 unsigned int smcfs, clk = 0; 104 105 acsr = ACSR; 106 107 smcfs = (acsr >> 23) & 0x7; 108 clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK; 109 110 return (clk / 10000); 111 } 112 113 void pxa3xx_clear_reset_status(unsigned int mask) 114 { 115 /* RESET_STATUS_* has a 1:1 mapping with ARSR */ 116 ARSR = mask; 117 } 118 119 /* 120 * Return the current AC97 clock frequency. 121 */ 122 static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk) 123 { 124 unsigned long rate = 312000000; 125 unsigned long ac97_div; 126 127 ac97_div = AC97_DIV; 128 129 /* This may loose precision for some rates but won't for the 130 * standard 24.576MHz. 131 */ 132 rate /= (ac97_div >> 12) & 0x7fff; 133 rate *= (ac97_div & 0xfff); 134 135 return rate; 136 } 137 138 /* 139 * Return the current HSIO bus clock frequency 140 */ 141 static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) 142 { 143 unsigned long acsr; 144 unsigned int hss, hsio_clk; 145 146 acsr = ACSR; 147 148 hss = (acsr >> 14) & 0x3; 149 hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK; 150 151 return hsio_clk; 152 } 153 154 void clk_pxa3xx_cken_enable(struct clk *clk) 155 { 156 unsigned long mask = 1ul << (clk->cken & 0x1f); 157 158 if (clk->cken < 32) 159 CKENA |= mask; 160 else 161 CKENB |= mask; 162 } 163 164 void clk_pxa3xx_cken_disable(struct clk *clk) 165 { 166 unsigned long mask = 1ul << (clk->cken & 0x1f); 167 168 if (clk->cken < 32) 169 CKENA &= ~mask; 170 else 171 CKENB &= ~mask; 172 } 173 174 const struct clkops clk_pxa3xx_cken_ops = { 175 .enable = clk_pxa3xx_cken_enable, 176 .disable = clk_pxa3xx_cken_disable, 177 }; 178 179 static const struct clkops clk_pxa3xx_hsio_ops = { 180 .enable = clk_pxa3xx_cken_enable, 181 .disable = clk_pxa3xx_cken_disable, 182 .getrate = clk_pxa3xx_hsio_getrate, 183 }; 184 185 static const struct clkops clk_pxa3xx_ac97_ops = { 186 .enable = clk_pxa3xx_cken_enable, 187 .disable = clk_pxa3xx_cken_disable, 188 .getrate = clk_pxa3xx_ac97_getrate, 189 }; 190 191 static void clk_pout_enable(struct clk *clk) 192 { 193 OSCC |= OSCC_PEN; 194 } 195 196 static void clk_pout_disable(struct clk *clk) 197 { 198 OSCC &= ~OSCC_PEN; 199 } 200 201 static const struct clkops clk_pout_ops = { 202 .enable = clk_pout_enable, 203 .disable = clk_pout_disable, 204 }; 205 206 static void clk_dummy_enable(struct clk *clk) 207 { 208 } 209 210 static void clk_dummy_disable(struct clk *clk) 211 { 212 } 213 214 static const struct clkops clk_dummy_ops = { 215 .enable = clk_dummy_enable, 216 .disable = clk_dummy_disable, 217 }; 218 219 static struct clk pxa3xx_clks[] = { 220 { 221 .name = "CLK_POUT", 222 .ops = &clk_pout_ops, 223 .rate = 13000000, 224 .delay = 70, 225 }, 226 227 /* Power I2C clock is always on */ 228 { 229 .name = "I2CCLK", 230 .ops = &clk_dummy_ops, 231 .dev = &pxa3xx_device_i2c_power.dev, 232 }, 233 234 PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev), 235 PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL), 236 PXA3xx_CK("AC97CLK", AC97, &clk_pxa3xx_ac97_ops, NULL), 237 238 PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), 239 PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), 240 PXA3xx_CKEN("UARTCLK", STUART, 14857000, 1, NULL), 241 242 PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), 243 PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa27x_device_udc.dev), 244 PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev), 245 PXA3xx_CKEN("KBDCLK", KEYPAD, 32768, 0, &pxa27x_device_keypad.dev), 246 247 PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), 248 PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), 249 PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev), 250 PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev), 251 PXA3xx_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev), 252 PXA3xx_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev), 253 254 PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev), 255 PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev), 256 }; 257 258 #ifdef CONFIG_PM 259 260 #define ISRAM_START 0x5c000000 261 #define ISRAM_SIZE SZ_256K 262 263 static void __iomem *sram; 264 static unsigned long wakeup_src; 265 266 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 267 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 268 269 enum { SLEEP_SAVE_CKENA, 270 SLEEP_SAVE_CKENB, 271 SLEEP_SAVE_ACCR, 272 273 SLEEP_SAVE_COUNT, 274 }; 275 276 static void pxa3xx_cpu_pm_save(unsigned long *sleep_save) 277 { 278 SAVE(CKENA); 279 SAVE(CKENB); 280 SAVE(ACCR); 281 } 282 283 static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save) 284 { 285 RESTORE(ACCR); 286 RESTORE(CKENA); 287 RESTORE(CKENB); 288 } 289 290 /* 291 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic 292 * memory controller has to be reinitialised, so we place some code 293 * in the SRAM to perform this function. 294 * 295 * We disable FIQs across the standby - otherwise, we might receive a 296 * FIQ while the SDRAM is unavailable. 297 */ 298 static void pxa3xx_cpu_standby(unsigned int pwrmode) 299 { 300 extern const char pm_enter_standby_start[], pm_enter_standby_end[]; 301 void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); 302 303 memcpy_toio(sram + 0x8000, pm_enter_standby_start, 304 pm_enter_standby_end - pm_enter_standby_start); 305 306 AD2D0SR = ~0; 307 AD2D1SR = ~0; 308 AD2D0ER = wakeup_src; 309 AD2D1ER = 0; 310 ASCR = ASCR; 311 ARSR = ARSR; 312 313 local_fiq_disable(); 314 fn(pwrmode); 315 local_fiq_enable(); 316 317 AD2D0ER = 0; 318 AD2D1ER = 0; 319 } 320 321 /* 322 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with 323 * PXA3xx development kits assumes that the resuming process continues 324 * with the address stored within the first 4 bytes of SDRAM. The PSPR 325 * register is used privately by BootROM and OBM, and _must_ be set to 326 * 0x5c014000 for the moment. 327 */ 328 static void pxa3xx_cpu_pm_suspend(void) 329 { 330 volatile unsigned long *p = (volatile void *)0xc0000000; 331 unsigned long saved_data = *p; 332 333 extern void pxa3xx_cpu_suspend(void); 334 extern void pxa3xx_cpu_resume(void); 335 336 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ 337 CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); 338 CKENB |= 1 << (CKEN_HSIO2 & 0x1f); 339 340 /* clear and setup wakeup source */ 341 AD3SR = ~0; 342 AD3ER = wakeup_src; 343 ASCR = ASCR; 344 ARSR = ARSR; 345 346 PCFR |= (1u << 13); /* L1_DIS */ 347 PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ 348 349 PSPR = 0x5c014000; 350 351 /* overwrite with the resume address */ 352 *p = virt_to_phys(pxa3xx_cpu_resume); 353 354 pxa3xx_cpu_suspend(); 355 356 *p = saved_data; 357 358 AD3ER = 0; 359 } 360 361 static void pxa3xx_cpu_pm_enter(suspend_state_t state) 362 { 363 /* 364 * Don't sleep if no wakeup sources are defined 365 */ 366 if (wakeup_src == 0) { 367 printk(KERN_ERR "Not suspending: no wakeup sources\n"); 368 return; 369 } 370 371 switch (state) { 372 case PM_SUSPEND_STANDBY: 373 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); 374 break; 375 376 case PM_SUSPEND_MEM: 377 pxa3xx_cpu_pm_suspend(); 378 break; 379 } 380 } 381 382 static int pxa3xx_cpu_pm_valid(suspend_state_t state) 383 { 384 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 385 } 386 387 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { 388 .save_count = SLEEP_SAVE_COUNT, 389 .save = pxa3xx_cpu_pm_save, 390 .restore = pxa3xx_cpu_pm_restore, 391 .valid = pxa3xx_cpu_pm_valid, 392 .enter = pxa3xx_cpu_pm_enter, 393 }; 394 395 static void __init pxa3xx_init_pm(void) 396 { 397 sram = ioremap(ISRAM_START, ISRAM_SIZE); 398 if (!sram) { 399 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); 400 return; 401 } 402 403 /* 404 * Since we copy wakeup code into the SRAM, we need to ensure 405 * that it is preserved over the low power modes. Note: bit 8 406 * is undocumented in the developer manual, but must be set. 407 */ 408 AD1R |= ADXR_L2 | ADXR_R0; 409 AD2R |= ADXR_L2 | ADXR_R0; 410 AD3R |= ADXR_L2 | ADXR_R0; 411 412 /* 413 * Clear the resume enable registers. 414 */ 415 AD1D0ER = 0; 416 AD2D0ER = 0; 417 AD2D1ER = 0; 418 AD3ER = 0; 419 420 pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; 421 } 422 423 static int pxa3xx_set_wake(unsigned int irq, unsigned int on) 424 { 425 unsigned long flags, mask = 0; 426 427 switch (irq) { 428 case IRQ_SSP3: 429 mask = ADXER_MFP_WSSP3; 430 break; 431 case IRQ_MSL: 432 mask = ADXER_WMSL0; 433 break; 434 case IRQ_USBH2: 435 case IRQ_USBH1: 436 mask = ADXER_WUSBH; 437 break; 438 case IRQ_KEYPAD: 439 mask = ADXER_WKP; 440 break; 441 case IRQ_AC97: 442 mask = ADXER_MFP_WAC97; 443 break; 444 case IRQ_USIM: 445 mask = ADXER_WUSIM0; 446 break; 447 case IRQ_SSP2: 448 mask = ADXER_MFP_WSSP2; 449 break; 450 case IRQ_I2C: 451 mask = ADXER_MFP_WI2C; 452 break; 453 case IRQ_STUART: 454 mask = ADXER_MFP_WUART3; 455 break; 456 case IRQ_BTUART: 457 mask = ADXER_MFP_WUART2; 458 break; 459 case IRQ_FFUART: 460 mask = ADXER_MFP_WUART1; 461 break; 462 case IRQ_MMC: 463 mask = ADXER_MFP_WMMC1; 464 break; 465 case IRQ_SSP: 466 mask = ADXER_MFP_WSSP1; 467 break; 468 case IRQ_RTCAlrm: 469 mask = ADXER_WRTC; 470 break; 471 case IRQ_SSP4: 472 mask = ADXER_MFP_WSSP4; 473 break; 474 case IRQ_TSI: 475 mask = ADXER_WTSI; 476 break; 477 case IRQ_USIM2: 478 mask = ADXER_WUSIM1; 479 break; 480 case IRQ_MMC2: 481 mask = ADXER_MFP_WMMC2; 482 break; 483 case IRQ_NAND: 484 mask = ADXER_MFP_WFLASH; 485 break; 486 case IRQ_USB2: 487 mask = ADXER_WUSB2; 488 break; 489 case IRQ_WAKEUP0: 490 mask = ADXER_WEXTWAKE0; 491 break; 492 case IRQ_WAKEUP1: 493 mask = ADXER_WEXTWAKE1; 494 break; 495 case IRQ_MMC3: 496 mask = ADXER_MFP_GEN12; 497 break; 498 default: 499 return -EINVAL; 500 } 501 502 local_irq_save(flags); 503 if (on) 504 wakeup_src |= mask; 505 else 506 wakeup_src &= ~mask; 507 local_irq_restore(flags); 508 509 return 0; 510 } 511 #else 512 static inline void pxa3xx_init_pm(void) {} 513 #define pxa3xx_set_wake NULL 514 #endif 515 516 void __init pxa3xx_init_irq(void) 517 { 518 /* enable CP6 access */ 519 u32 value; 520 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); 521 value |= (1 << 6); 522 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); 523 524 pxa_init_irq(56, pxa3xx_set_wake); 525 pxa_init_gpio(128, NULL); 526 } 527 528 /* 529 * device registration specific to PXA3xx. 530 */ 531 532 static struct resource i2c_power_resources[] = { 533 { 534 .start = 0x40f500c0, 535 .end = 0x40f500d3, 536 .flags = IORESOURCE_MEM, 537 }, { 538 .start = IRQ_PWRI2C, 539 .end = IRQ_PWRI2C, 540 .flags = IORESOURCE_IRQ, 541 }, 542 }; 543 544 struct platform_device pxa3xx_device_i2c_power = { 545 .name = "pxa2xx-i2c", 546 .id = 1, 547 .resource = i2c_power_resources, 548 .num_resources = ARRAY_SIZE(i2c_power_resources), 549 }; 550 551 void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) 552 { 553 pxa3xx_device_i2c_power.dev.platform_data = info; 554 } 555 556 static struct platform_device *devices[] __initdata = { 557 /* &pxa_device_udc, The UDC driver is PXA25x only */ 558 &pxa_device_ffuart, 559 &pxa_device_btuart, 560 &pxa_device_stuart, 561 &pxa_device_i2s, 562 &pxa_device_rtc, 563 &pxa27x_device_ssp1, 564 &pxa27x_device_ssp2, 565 &pxa27x_device_ssp3, 566 &pxa3xx_device_ssp4, 567 &pxa27x_device_pwm0, 568 &pxa27x_device_pwm1, 569 &pxa3xx_device_i2c_power, 570 }; 571 572 static struct sys_device pxa3xx_sysdev[] = { 573 { 574 .cls = &pxa_irq_sysclass, 575 }, { 576 .cls = &pxa3xx_mfp_sysclass, 577 }, { 578 .cls = &pxa_gpio_sysclass, 579 }, 580 }; 581 582 static int __init pxa3xx_init(void) 583 { 584 int i, ret = 0; 585 586 if (cpu_is_pxa3xx()) { 587 588 reset_status = ARSR; 589 590 /* 591 * clear RDH bit every time after reset 592 * 593 * Note: the last 3 bits DxS are write-1-to-clear so carefully 594 * preserve them here in case they will be referenced later 595 */ 596 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); 597 598 clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks)); 599 600 if ((ret = pxa_init_dma(32))) 601 return ret; 602 603 pxa3xx_init_pm(); 604 605 for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) { 606 ret = sysdev_register(&pxa3xx_sysdev[i]); 607 if (ret) 608 pr_err("failed to register sysdev[%d]\n", i); 609 } 610 611 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 612 } 613 614 return ret; 615 } 616 617 postcore_initcall(pxa3xx_init); 618