1 /* 2 * linux/arch/arm/mach-pxa/pxa3xx.c 3 * 4 * code specific to pxa3xx aka Monahans 5 * 6 * Copyright (C) 2006 Marvell International Ltd. 7 * 8 * 2007-09-02: eric miao <eric.miao@marvell.com> 9 * initial version 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/kernel.h> 18 #include <linux/init.h> 19 #include <linux/pm.h> 20 #include <linux/platform_device.h> 21 #include <linux/irq.h> 22 #include <linux/io.h> 23 #include <linux/sysdev.h> 24 25 #include <mach/hardware.h> 26 #include <mach/pxa3xx-regs.h> 27 #include <mach/reset.h> 28 #include <mach/ohci.h> 29 #include <mach/pm.h> 30 #include <mach/dma.h> 31 #include <mach/ssp.h> 32 33 #include "generic.h" 34 #include "devices.h" 35 #include "clock.h" 36 37 /* Crystal clock: 13MHz */ 38 #define BASE_CLK 13000000 39 40 /* Ring Oscillator Clock: 60MHz */ 41 #define RO_CLK 60000000 42 43 #define ACCR_D0CS (1 << 26) 44 #define ACCR_PCCE (1 << 11) 45 46 /* crystal frequency to static memory controller multiplier (SMCFS) */ 47 static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; 48 49 /* crystal frequency to HSIO bus frequency multiplier (HSS) */ 50 static unsigned char hss_mult[4] = { 8, 12, 16, 0 }; 51 52 /* 53 * Get the clock frequency as reflected by CCSR and the turbo flag. 54 * We assume these values have been applied via a fcs. 55 * If info is not 0 we also display the current settings. 56 */ 57 unsigned int pxa3xx_get_clk_frequency_khz(int info) 58 { 59 unsigned long acsr, xclkcfg; 60 unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS; 61 62 /* Read XCLKCFG register turbo bit */ 63 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); 64 t = xclkcfg & 0x1; 65 66 acsr = ACSR; 67 68 xl = acsr & 0x1f; 69 xn = (acsr >> 8) & 0x7; 70 hss = (acsr >> 14) & 0x3; 71 72 XL = xl * BASE_CLK; 73 XN = xn * XL; 74 75 ro = acsr & ACCR_D0CS; 76 77 CLK = (ro) ? RO_CLK : ((t) ? XN : XL); 78 HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK; 79 80 if (info) { 81 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n", 82 RO_CLK / 1000000, (RO_CLK % 1000000) / 10000, 83 (ro) ? "" : "in"); 84 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n", 85 XL / 1000000, (XL % 1000000) / 10000, xl); 86 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n", 87 XN / 1000000, (XN % 1000000) / 10000, xn, 88 (t) ? "" : "in"); 89 pr_info("HSIO bus clock: %d.%02dMHz\n", 90 HSS / 1000000, (HSS % 1000000) / 10000); 91 } 92 93 return CLK / 1000; 94 } 95 96 /* 97 * Return the current static memory controller clock frequency 98 * in units of 10kHz 99 */ 100 unsigned int pxa3xx_get_memclk_frequency_10khz(void) 101 { 102 unsigned long acsr; 103 unsigned int smcfs, clk = 0; 104 105 acsr = ACSR; 106 107 smcfs = (acsr >> 23) & 0x7; 108 clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK; 109 110 return (clk / 10000); 111 } 112 113 void pxa3xx_clear_reset_status(unsigned int mask) 114 { 115 /* RESET_STATUS_* has a 1:1 mapping with ARSR */ 116 ARSR = mask; 117 } 118 119 /* 120 * Return the current AC97 clock frequency. 121 */ 122 static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk) 123 { 124 unsigned long rate = 312000000; 125 unsigned long ac97_div; 126 127 ac97_div = AC97_DIV; 128 129 /* This may loose precision for some rates but won't for the 130 * standard 24.576MHz. 131 */ 132 rate /= (ac97_div >> 12) & 0x7fff; 133 rate *= (ac97_div & 0xfff); 134 135 return rate; 136 } 137 138 /* 139 * Return the current HSIO bus clock frequency 140 */ 141 static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) 142 { 143 unsigned long acsr; 144 unsigned int hss, hsio_clk; 145 146 acsr = ACSR; 147 148 hss = (acsr >> 14) & 0x3; 149 hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK; 150 151 return hsio_clk; 152 } 153 154 void clk_pxa3xx_cken_enable(struct clk *clk) 155 { 156 unsigned long mask = 1ul << (clk->cken & 0x1f); 157 158 if (clk->cken < 32) 159 CKENA |= mask; 160 else 161 CKENB |= mask; 162 } 163 164 void clk_pxa3xx_cken_disable(struct clk *clk) 165 { 166 unsigned long mask = 1ul << (clk->cken & 0x1f); 167 168 if (clk->cken < 32) 169 CKENA &= ~mask; 170 else 171 CKENB &= ~mask; 172 } 173 174 const struct clkops clk_pxa3xx_cken_ops = { 175 .enable = clk_pxa3xx_cken_enable, 176 .disable = clk_pxa3xx_cken_disable, 177 }; 178 179 static const struct clkops clk_pxa3xx_hsio_ops = { 180 .enable = clk_pxa3xx_cken_enable, 181 .disable = clk_pxa3xx_cken_disable, 182 .getrate = clk_pxa3xx_hsio_getrate, 183 }; 184 185 static const struct clkops clk_pxa3xx_ac97_ops = { 186 .enable = clk_pxa3xx_cken_enable, 187 .disable = clk_pxa3xx_cken_disable, 188 .getrate = clk_pxa3xx_ac97_getrate, 189 }; 190 191 static void clk_pout_enable(struct clk *clk) 192 { 193 OSCC |= OSCC_PEN; 194 } 195 196 static void clk_pout_disable(struct clk *clk) 197 { 198 OSCC &= ~OSCC_PEN; 199 } 200 201 static const struct clkops clk_pout_ops = { 202 .enable = clk_pout_enable, 203 .disable = clk_pout_disable, 204 }; 205 206 static void clk_dummy_enable(struct clk *clk) 207 { 208 } 209 210 static void clk_dummy_disable(struct clk *clk) 211 { 212 } 213 214 static const struct clkops clk_dummy_ops = { 215 .enable = clk_dummy_enable, 216 .disable = clk_dummy_disable, 217 }; 218 219 static struct clk clk_pxa3xx_pout = { 220 .ops = &clk_pout_ops, 221 .rate = 13000000, 222 .delay = 70, 223 }; 224 225 static struct clk clk_dummy = { 226 .ops = &clk_dummy_ops, 227 }; 228 229 static DEFINE_PXA3_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops); 230 static DEFINE_PXA3_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops); 231 static DEFINE_PXA3_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops); 232 static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); 233 static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); 234 static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); 235 static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0); 236 static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5); 237 static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0); 238 static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0); 239 static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0); 240 static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0); 241 static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0); 242 static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0); 243 static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0); 244 static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0); 245 static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0); 246 static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0); 247 248 static struct clk_lookup pxa3xx_clkregs[] = { 249 INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), 250 /* Power I2C clock is always on */ 251 INIT_CLKREG(&clk_dummy, "pxa2xx-i2c.1", NULL), 252 INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL), 253 INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"), 254 INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"), 255 INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL), 256 INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL), 257 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL), 258 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"), 259 INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL), 260 INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL), 261 INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL), 262 INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL), 263 INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL), 264 INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL), 265 INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL), 266 INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL), 267 INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL), 268 INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL), 269 INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL), 270 INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL), 271 }; 272 273 #ifdef CONFIG_PM 274 275 #define ISRAM_START 0x5c000000 276 #define ISRAM_SIZE SZ_256K 277 278 static void __iomem *sram; 279 static unsigned long wakeup_src; 280 281 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 282 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 283 284 enum { SLEEP_SAVE_CKENA, 285 SLEEP_SAVE_CKENB, 286 SLEEP_SAVE_ACCR, 287 288 SLEEP_SAVE_COUNT, 289 }; 290 291 static void pxa3xx_cpu_pm_save(unsigned long *sleep_save) 292 { 293 SAVE(CKENA); 294 SAVE(CKENB); 295 SAVE(ACCR); 296 } 297 298 static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save) 299 { 300 RESTORE(ACCR); 301 RESTORE(CKENA); 302 RESTORE(CKENB); 303 } 304 305 /* 306 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic 307 * memory controller has to be reinitialised, so we place some code 308 * in the SRAM to perform this function. 309 * 310 * We disable FIQs across the standby - otherwise, we might receive a 311 * FIQ while the SDRAM is unavailable. 312 */ 313 static void pxa3xx_cpu_standby(unsigned int pwrmode) 314 { 315 extern const char pm_enter_standby_start[], pm_enter_standby_end[]; 316 void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); 317 318 memcpy_toio(sram + 0x8000, pm_enter_standby_start, 319 pm_enter_standby_end - pm_enter_standby_start); 320 321 AD2D0SR = ~0; 322 AD2D1SR = ~0; 323 AD2D0ER = wakeup_src; 324 AD2D1ER = 0; 325 ASCR = ASCR; 326 ARSR = ARSR; 327 328 local_fiq_disable(); 329 fn(pwrmode); 330 local_fiq_enable(); 331 332 AD2D0ER = 0; 333 AD2D1ER = 0; 334 } 335 336 /* 337 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with 338 * PXA3xx development kits assumes that the resuming process continues 339 * with the address stored within the first 4 bytes of SDRAM. The PSPR 340 * register is used privately by BootROM and OBM, and _must_ be set to 341 * 0x5c014000 for the moment. 342 */ 343 static void pxa3xx_cpu_pm_suspend(void) 344 { 345 volatile unsigned long *p = (volatile void *)0xc0000000; 346 unsigned long saved_data = *p; 347 348 extern void pxa3xx_cpu_suspend(void); 349 extern void pxa3xx_cpu_resume(void); 350 351 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ 352 CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); 353 CKENB |= 1 << (CKEN_HSIO2 & 0x1f); 354 355 /* clear and setup wakeup source */ 356 AD3SR = ~0; 357 AD3ER = wakeup_src; 358 ASCR = ASCR; 359 ARSR = ARSR; 360 361 PCFR |= (1u << 13); /* L1_DIS */ 362 PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ 363 364 PSPR = 0x5c014000; 365 366 /* overwrite with the resume address */ 367 *p = virt_to_phys(pxa3xx_cpu_resume); 368 369 pxa3xx_cpu_suspend(); 370 371 *p = saved_data; 372 373 AD3ER = 0; 374 } 375 376 static void pxa3xx_cpu_pm_enter(suspend_state_t state) 377 { 378 /* 379 * Don't sleep if no wakeup sources are defined 380 */ 381 if (wakeup_src == 0) { 382 printk(KERN_ERR "Not suspending: no wakeup sources\n"); 383 return; 384 } 385 386 switch (state) { 387 case PM_SUSPEND_STANDBY: 388 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); 389 break; 390 391 case PM_SUSPEND_MEM: 392 pxa3xx_cpu_pm_suspend(); 393 break; 394 } 395 } 396 397 static int pxa3xx_cpu_pm_valid(suspend_state_t state) 398 { 399 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 400 } 401 402 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { 403 .save_count = SLEEP_SAVE_COUNT, 404 .save = pxa3xx_cpu_pm_save, 405 .restore = pxa3xx_cpu_pm_restore, 406 .valid = pxa3xx_cpu_pm_valid, 407 .enter = pxa3xx_cpu_pm_enter, 408 }; 409 410 static void __init pxa3xx_init_pm(void) 411 { 412 sram = ioremap(ISRAM_START, ISRAM_SIZE); 413 if (!sram) { 414 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); 415 return; 416 } 417 418 /* 419 * Since we copy wakeup code into the SRAM, we need to ensure 420 * that it is preserved over the low power modes. Note: bit 8 421 * is undocumented in the developer manual, but must be set. 422 */ 423 AD1R |= ADXR_L2 | ADXR_R0; 424 AD2R |= ADXR_L2 | ADXR_R0; 425 AD3R |= ADXR_L2 | ADXR_R0; 426 427 /* 428 * Clear the resume enable registers. 429 */ 430 AD1D0ER = 0; 431 AD2D0ER = 0; 432 AD2D1ER = 0; 433 AD3ER = 0; 434 435 pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; 436 } 437 438 static int pxa3xx_set_wake(unsigned int irq, unsigned int on) 439 { 440 unsigned long flags, mask = 0; 441 442 switch (irq) { 443 case IRQ_SSP3: 444 mask = ADXER_MFP_WSSP3; 445 break; 446 case IRQ_MSL: 447 mask = ADXER_WMSL0; 448 break; 449 case IRQ_USBH2: 450 case IRQ_USBH1: 451 mask = ADXER_WUSBH; 452 break; 453 case IRQ_KEYPAD: 454 mask = ADXER_WKP; 455 break; 456 case IRQ_AC97: 457 mask = ADXER_MFP_WAC97; 458 break; 459 case IRQ_USIM: 460 mask = ADXER_WUSIM0; 461 break; 462 case IRQ_SSP2: 463 mask = ADXER_MFP_WSSP2; 464 break; 465 case IRQ_I2C: 466 mask = ADXER_MFP_WI2C; 467 break; 468 case IRQ_STUART: 469 mask = ADXER_MFP_WUART3; 470 break; 471 case IRQ_BTUART: 472 mask = ADXER_MFP_WUART2; 473 break; 474 case IRQ_FFUART: 475 mask = ADXER_MFP_WUART1; 476 break; 477 case IRQ_MMC: 478 mask = ADXER_MFP_WMMC1; 479 break; 480 case IRQ_SSP: 481 mask = ADXER_MFP_WSSP1; 482 break; 483 case IRQ_RTCAlrm: 484 mask = ADXER_WRTC; 485 break; 486 case IRQ_SSP4: 487 mask = ADXER_MFP_WSSP4; 488 break; 489 case IRQ_TSI: 490 mask = ADXER_WTSI; 491 break; 492 case IRQ_USIM2: 493 mask = ADXER_WUSIM1; 494 break; 495 case IRQ_MMC2: 496 mask = ADXER_MFP_WMMC2; 497 break; 498 case IRQ_NAND: 499 mask = ADXER_MFP_WFLASH; 500 break; 501 case IRQ_USB2: 502 mask = ADXER_WUSB2; 503 break; 504 case IRQ_WAKEUP0: 505 mask = ADXER_WEXTWAKE0; 506 break; 507 case IRQ_WAKEUP1: 508 mask = ADXER_WEXTWAKE1; 509 break; 510 case IRQ_MMC3: 511 mask = ADXER_MFP_GEN12; 512 break; 513 default: 514 return -EINVAL; 515 } 516 517 local_irq_save(flags); 518 if (on) 519 wakeup_src |= mask; 520 else 521 wakeup_src &= ~mask; 522 local_irq_restore(flags); 523 524 return 0; 525 } 526 #else 527 static inline void pxa3xx_init_pm(void) {} 528 #define pxa3xx_set_wake NULL 529 #endif 530 531 void __init pxa3xx_init_irq(void) 532 { 533 /* enable CP6 access */ 534 u32 value; 535 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); 536 value |= (1 << 6); 537 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); 538 539 pxa_init_irq(56, pxa3xx_set_wake); 540 pxa_init_gpio(128, NULL); 541 } 542 543 /* 544 * device registration specific to PXA3xx. 545 */ 546 547 static struct resource i2c_power_resources[] = { 548 { 549 .start = 0x40f500c0, 550 .end = 0x40f500d3, 551 .flags = IORESOURCE_MEM, 552 }, { 553 .start = IRQ_PWRI2C, 554 .end = IRQ_PWRI2C, 555 .flags = IORESOURCE_IRQ, 556 }, 557 }; 558 559 struct platform_device pxa3xx_device_i2c_power = { 560 .name = "pxa2xx-i2c", 561 .id = 1, 562 .resource = i2c_power_resources, 563 .num_resources = ARRAY_SIZE(i2c_power_resources), 564 }; 565 566 void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) 567 { 568 pxa3xx_device_i2c_power.dev.platform_data = info; 569 } 570 571 static struct platform_device *devices[] __initdata = { 572 /* &pxa_device_udc, The UDC driver is PXA25x only */ 573 &pxa_device_ffuart, 574 &pxa_device_btuart, 575 &pxa_device_stuart, 576 &pxa_device_i2s, 577 &pxa_device_rtc, 578 &pxa27x_device_ssp1, 579 &pxa27x_device_ssp2, 580 &pxa27x_device_ssp3, 581 &pxa3xx_device_ssp4, 582 &pxa27x_device_pwm0, 583 &pxa27x_device_pwm1, 584 &pxa3xx_device_i2c_power, 585 }; 586 587 static struct sys_device pxa3xx_sysdev[] = { 588 { 589 .cls = &pxa_irq_sysclass, 590 }, { 591 .cls = &pxa3xx_mfp_sysclass, 592 }, { 593 .cls = &pxa_gpio_sysclass, 594 }, 595 }; 596 597 static int __init pxa3xx_init(void) 598 { 599 int i, ret = 0; 600 601 if (cpu_is_pxa3xx()) { 602 603 reset_status = ARSR; 604 605 /* 606 * clear RDH bit every time after reset 607 * 608 * Note: the last 3 bits DxS are write-1-to-clear so carefully 609 * preserve them here in case they will be referenced later 610 */ 611 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); 612 613 clks_register(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs)); 614 615 if ((ret = pxa_init_dma(32))) 616 return ret; 617 618 pxa3xx_init_pm(); 619 620 for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) { 621 ret = sysdev_register(&pxa3xx_sysdev[i]); 622 if (ret) 623 pr_err("failed to register sysdev[%d]\n", i); 624 } 625 626 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 627 } 628 629 return ret; 630 } 631 632 postcore_initcall(pxa3xx_init); 633