1 /* 2 * linux/arch/arm/mach-pxa/pxa3xx.c 3 * 4 * code specific to pxa3xx aka Monahans 5 * 6 * Copyright (C) 2006 Marvell International Ltd. 7 * 8 * 2007-09-02: eric miao <eric.miao@marvell.com> 9 * initial version 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/kernel.h> 18 #include <linux/init.h> 19 #include <linux/pm.h> 20 #include <linux/platform_device.h> 21 #include <linux/irq.h> 22 #include <linux/io.h> 23 #include <linux/sysdev.h> 24 25 #include <asm/hardware.h> 26 #include <asm/arch/pxa3xx-regs.h> 27 #include <asm/arch/ohci.h> 28 #include <asm/arch/pm.h> 29 #include <asm/arch/dma.h> 30 #include <asm/arch/ssp.h> 31 32 #include "generic.h" 33 #include "devices.h" 34 #include "clock.h" 35 36 /* Crystal clock: 13MHz */ 37 #define BASE_CLK 13000000 38 39 /* Ring Oscillator Clock: 60MHz */ 40 #define RO_CLK 60000000 41 42 #define ACCR_D0CS (1 << 26) 43 #define ACCR_PCCE (1 << 11) 44 45 /* crystal frequency to static memory controller multiplier (SMCFS) */ 46 static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; 47 48 /* crystal frequency to HSIO bus frequency multiplier (HSS) */ 49 static unsigned char hss_mult[4] = { 8, 12, 16, 0 }; 50 51 /* 52 * Get the clock frequency as reflected by CCSR and the turbo flag. 53 * We assume these values have been applied via a fcs. 54 * If info is not 0 we also display the current settings. 55 */ 56 unsigned int pxa3xx_get_clk_frequency_khz(int info) 57 { 58 unsigned long acsr, xclkcfg; 59 unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS; 60 61 /* Read XCLKCFG register turbo bit */ 62 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); 63 t = xclkcfg & 0x1; 64 65 acsr = ACSR; 66 67 xl = acsr & 0x1f; 68 xn = (acsr >> 8) & 0x7; 69 hss = (acsr >> 14) & 0x3; 70 71 XL = xl * BASE_CLK; 72 XN = xn * XL; 73 74 ro = acsr & ACCR_D0CS; 75 76 CLK = (ro) ? RO_CLK : ((t) ? XN : XL); 77 HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK; 78 79 if (info) { 80 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n", 81 RO_CLK / 1000000, (RO_CLK % 1000000) / 10000, 82 (ro) ? "" : "in"); 83 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n", 84 XL / 1000000, (XL % 1000000) / 10000, xl); 85 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n", 86 XN / 1000000, (XN % 1000000) / 10000, xn, 87 (t) ? "" : "in"); 88 pr_info("HSIO bus clock: %d.%02dMHz\n", 89 HSS / 1000000, (HSS % 1000000) / 10000); 90 } 91 92 return CLK / 1000; 93 } 94 95 /* 96 * Return the current static memory controller clock frequency 97 * in units of 10kHz 98 */ 99 unsigned int pxa3xx_get_memclk_frequency_10khz(void) 100 { 101 unsigned long acsr; 102 unsigned int smcfs, clk = 0; 103 104 acsr = ACSR; 105 106 smcfs = (acsr >> 23) & 0x7; 107 clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK; 108 109 return (clk / 10000); 110 } 111 112 /* 113 * Return the current HSIO bus clock frequency 114 */ 115 static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) 116 { 117 unsigned long acsr; 118 unsigned int hss, hsio_clk; 119 120 acsr = ACSR; 121 122 hss = (acsr >> 14) & 0x3; 123 hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK; 124 125 return hsio_clk; 126 } 127 128 static void clk_pxa3xx_cken_enable(struct clk *clk) 129 { 130 unsigned long mask = 1ul << (clk->cken & 0x1f); 131 132 local_irq_disable(); 133 134 if (clk->cken < 32) 135 CKENA |= mask; 136 else 137 CKENB |= mask; 138 139 local_irq_enable(); 140 } 141 142 static void clk_pxa3xx_cken_disable(struct clk *clk) 143 { 144 unsigned long mask = 1ul << (clk->cken & 0x1f); 145 146 local_irq_disable(); 147 148 if (clk->cken < 32) 149 CKENA &= ~mask; 150 else 151 CKENB &= ~mask; 152 153 local_irq_enable(); 154 } 155 156 static const struct clkops clk_pxa3xx_cken_ops = { 157 .enable = clk_pxa3xx_cken_enable, 158 .disable = clk_pxa3xx_cken_disable, 159 }; 160 161 static const struct clkops clk_pxa3xx_hsio_ops = { 162 .enable = clk_pxa3xx_cken_enable, 163 .disable = clk_pxa3xx_cken_disable, 164 .getrate = clk_pxa3xx_hsio_getrate, 165 }; 166 167 #define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev) \ 168 { \ 169 .name = _name, \ 170 .dev = _dev, \ 171 .ops = &clk_pxa3xx_cken_ops, \ 172 .rate = _rate, \ 173 .cken = CKEN_##_cken, \ 174 .delay = _delay, \ 175 } 176 177 #define PXA3xx_CK(_name, _cken, _ops, _dev) \ 178 { \ 179 .name = _name, \ 180 .dev = _dev, \ 181 .ops = _ops, \ 182 .cken = CKEN_##_cken, \ 183 } 184 185 static struct clk pxa3xx_clks[] = { 186 PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev), 187 PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL), 188 189 PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), 190 PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), 191 PXA3xx_CKEN("UARTCLK", STUART, 14857000, 1, NULL), 192 193 PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), 194 PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev), 195 PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev), 196 197 PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), 198 PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), 199 PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev), 200 PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev), 201 202 PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev), 203 PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev), 204 PXA3xx_CKEN("MMCCLK", MMC3, 19500000, 0, &pxa3xx_device_mci3.dev), 205 }; 206 207 #ifdef CONFIG_PM 208 209 #define ISRAM_START 0x5c000000 210 #define ISRAM_SIZE SZ_256K 211 212 static void __iomem *sram; 213 static unsigned long wakeup_src; 214 215 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 216 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 217 218 enum { SLEEP_SAVE_START = 0, 219 SLEEP_SAVE_CKENA, 220 SLEEP_SAVE_CKENB, 221 SLEEP_SAVE_ACCR, 222 223 SLEEP_SAVE_SIZE, 224 }; 225 226 static void pxa3xx_cpu_pm_save(unsigned long *sleep_save) 227 { 228 SAVE(CKENA); 229 SAVE(CKENB); 230 SAVE(ACCR); 231 } 232 233 static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save) 234 { 235 RESTORE(ACCR); 236 RESTORE(CKENA); 237 RESTORE(CKENB); 238 } 239 240 /* 241 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic 242 * memory controller has to be reinitialised, so we place some code 243 * in the SRAM to perform this function. 244 * 245 * We disable FIQs across the standby - otherwise, we might receive a 246 * FIQ while the SDRAM is unavailable. 247 */ 248 static void pxa3xx_cpu_standby(unsigned int pwrmode) 249 { 250 extern const char pm_enter_standby_start[], pm_enter_standby_end[]; 251 void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); 252 253 memcpy_toio(sram + 0x8000, pm_enter_standby_start, 254 pm_enter_standby_end - pm_enter_standby_start); 255 256 AD2D0SR = ~0; 257 AD2D1SR = ~0; 258 AD2D0ER = wakeup_src; 259 AD2D1ER = 0; 260 ASCR = ASCR; 261 ARSR = ARSR; 262 263 local_fiq_disable(); 264 fn(pwrmode); 265 local_fiq_enable(); 266 267 AD2D0ER = 0; 268 AD2D1ER = 0; 269 } 270 271 /* 272 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with 273 * PXA3xx development kits assumes that the resuming process continues 274 * with the address stored within the first 4 bytes of SDRAM. The PSPR 275 * register is used privately by BootROM and OBM, and _must_ be set to 276 * 0x5c014000 for the moment. 277 */ 278 static void pxa3xx_cpu_pm_suspend(void) 279 { 280 volatile unsigned long *p = (volatile void *)0xc0000000; 281 unsigned long saved_data = *p; 282 283 extern void pxa3xx_cpu_suspend(void); 284 extern void pxa3xx_cpu_resume(void); 285 286 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ 287 CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); 288 CKENB |= 1 << (CKEN_HSIO2 & 0x1f); 289 290 /* clear and setup wakeup source */ 291 AD3SR = ~0; 292 AD3ER = wakeup_src; 293 ASCR = ASCR; 294 ARSR = ARSR; 295 296 PCFR |= (1u << 13); /* L1_DIS */ 297 PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ 298 299 PSPR = 0x5c014000; 300 301 /* overwrite with the resume address */ 302 *p = virt_to_phys(pxa3xx_cpu_resume); 303 304 pxa3xx_cpu_suspend(); 305 306 *p = saved_data; 307 308 AD3ER = 0; 309 } 310 311 static void pxa3xx_cpu_pm_enter(suspend_state_t state) 312 { 313 /* 314 * Don't sleep if no wakeup sources are defined 315 */ 316 if (wakeup_src == 0) 317 return; 318 319 switch (state) { 320 case PM_SUSPEND_STANDBY: 321 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); 322 break; 323 324 case PM_SUSPEND_MEM: 325 pxa3xx_cpu_pm_suspend(); 326 break; 327 } 328 } 329 330 static int pxa3xx_cpu_pm_valid(suspend_state_t state) 331 { 332 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 333 } 334 335 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { 336 .save_size = SLEEP_SAVE_SIZE, 337 .save = pxa3xx_cpu_pm_save, 338 .restore = pxa3xx_cpu_pm_restore, 339 .valid = pxa3xx_cpu_pm_valid, 340 .enter = pxa3xx_cpu_pm_enter, 341 }; 342 343 static void __init pxa3xx_init_pm(void) 344 { 345 sram = ioremap(ISRAM_START, ISRAM_SIZE); 346 if (!sram) { 347 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); 348 return; 349 } 350 351 /* 352 * Since we copy wakeup code into the SRAM, we need to ensure 353 * that it is preserved over the low power modes. Note: bit 8 354 * is undocumented in the developer manual, but must be set. 355 */ 356 AD1R |= ADXR_L2 | ADXR_R0; 357 AD2R |= ADXR_L2 | ADXR_R0; 358 AD3R |= ADXR_L2 | ADXR_R0; 359 360 /* 361 * Clear the resume enable registers. 362 */ 363 AD1D0ER = 0; 364 AD2D0ER = 0; 365 AD2D1ER = 0; 366 AD3ER = 0; 367 368 pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; 369 } 370 371 static int pxa3xx_set_wake(unsigned int irq, unsigned int on) 372 { 373 unsigned long flags, mask = 0; 374 375 switch (irq) { 376 case IRQ_SSP3: 377 mask = ADXER_MFP_WSSP3; 378 break; 379 case IRQ_MSL: 380 mask = ADXER_WMSL0; 381 break; 382 case IRQ_USBH2: 383 case IRQ_USBH1: 384 mask = ADXER_WUSBH; 385 break; 386 case IRQ_KEYPAD: 387 mask = ADXER_WKP; 388 break; 389 case IRQ_AC97: 390 mask = ADXER_MFP_WAC97; 391 break; 392 case IRQ_USIM: 393 mask = ADXER_WUSIM0; 394 break; 395 case IRQ_SSP2: 396 mask = ADXER_MFP_WSSP2; 397 break; 398 case IRQ_I2C: 399 mask = ADXER_MFP_WI2C; 400 break; 401 case IRQ_STUART: 402 mask = ADXER_MFP_WUART3; 403 break; 404 case IRQ_BTUART: 405 mask = ADXER_MFP_WUART2; 406 break; 407 case IRQ_FFUART: 408 mask = ADXER_MFP_WUART1; 409 break; 410 case IRQ_MMC: 411 mask = ADXER_MFP_WMMC1; 412 break; 413 case IRQ_SSP: 414 mask = ADXER_MFP_WSSP1; 415 break; 416 case IRQ_RTCAlrm: 417 mask = ADXER_WRTC; 418 break; 419 case IRQ_SSP4: 420 mask = ADXER_MFP_WSSP4; 421 break; 422 case IRQ_TSI: 423 mask = ADXER_WTSI; 424 break; 425 case IRQ_USIM2: 426 mask = ADXER_WUSIM1; 427 break; 428 case IRQ_MMC2: 429 mask = ADXER_MFP_WMMC2; 430 break; 431 case IRQ_NAND: 432 mask = ADXER_MFP_WFLASH; 433 break; 434 case IRQ_USB2: 435 mask = ADXER_WUSB2; 436 break; 437 case IRQ_WAKEUP0: 438 mask = ADXER_WEXTWAKE0; 439 break; 440 case IRQ_WAKEUP1: 441 mask = ADXER_WEXTWAKE1; 442 break; 443 case IRQ_MMC3: 444 mask = ADXER_MFP_GEN12; 445 break; 446 } 447 448 local_irq_save(flags); 449 if (on) 450 wakeup_src |= mask; 451 else 452 wakeup_src &= ~mask; 453 local_irq_restore(flags); 454 455 return 0; 456 } 457 458 static void pxa3xx_init_irq_pm(void) 459 { 460 pxa_init_irq_set_wake(pxa3xx_set_wake); 461 } 462 463 #else 464 static inline void pxa3xx_init_pm(void) {} 465 static inline void pxa3xx_init_irq_pm(void) {} 466 #endif 467 468 void __init pxa3xx_init_irq(void) 469 { 470 /* enable CP6 access */ 471 u32 value; 472 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); 473 value |= (1 << 6); 474 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); 475 476 pxa_init_irq_low(); 477 pxa_init_irq_high(); 478 pxa_init_irq_gpio(128); 479 pxa3xx_init_irq_pm(); 480 } 481 482 /* 483 * device registration specific to PXA3xx. 484 */ 485 486 static struct platform_device *devices[] __initdata = { 487 &pxa_device_udc, 488 &pxa_device_ffuart, 489 &pxa_device_btuart, 490 &pxa_device_stuart, 491 &pxa_device_i2s, 492 &pxa_device_rtc, 493 &pxa27x_device_ssp1, 494 &pxa27x_device_ssp2, 495 &pxa27x_device_ssp3, 496 &pxa3xx_device_ssp4, 497 }; 498 499 static struct sys_device pxa3xx_sysdev[] = { 500 { 501 .id = 0, 502 .cls = &pxa_irq_sysclass, 503 }, { 504 .id = 1, 505 .cls = &pxa_irq_sysclass, 506 }, { 507 .cls = &pxa_gpio_sysclass, 508 }, 509 }; 510 511 static int __init pxa3xx_init(void) 512 { 513 int i, ret = 0; 514 515 if (cpu_is_pxa3xx()) { 516 /* 517 * clear RDH bit every time after reset 518 * 519 * Note: the last 3 bits DxS are write-1-to-clear so carefully 520 * preserve them here in case they will be referenced later 521 */ 522 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); 523 524 clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks)); 525 526 if ((ret = pxa_init_dma(32))) 527 return ret; 528 529 pxa3xx_init_pm(); 530 531 for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) { 532 ret = sysdev_register(&pxa3xx_sysdev[i]); 533 if (ret) 534 pr_err("failed to register sysdev[%d]\n", i); 535 } 536 537 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 538 } 539 540 return ret; 541 } 542 543 subsys_initcall(pxa3xx_init); 544