1 /* 2 * linux/arch/arm/mach-pxa/pxa3xx.c 3 * 4 * code specific to pxa3xx aka Monahans 5 * 6 * Copyright (C) 2006 Marvell International Ltd. 7 * 8 * 2007-09-02: eric miao <eric.miao@marvell.com> 9 * initial version 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/kernel.h> 18 #include <linux/init.h> 19 #include <linux/pm.h> 20 #include <linux/platform_device.h> 21 #include <linux/irq.h> 22 #include <linux/io.h> 23 #include <linux/sysdev.h> 24 25 #include <asm/mach/map.h> 26 #include <mach/hardware.h> 27 #include <mach/gpio.h> 28 #include <mach/pxa3xx-regs.h> 29 #include <mach/reset.h> 30 #include <mach/ohci.h> 31 #include <mach/pm.h> 32 #include <mach/dma.h> 33 #include <mach/regs-intc.h> 34 #include <plat/i2c.h> 35 36 #include "generic.h" 37 #include "devices.h" 38 #include "clock.h" 39 40 /* Crystal clock: 13MHz */ 41 #define BASE_CLK 13000000 42 43 /* Ring Oscillator Clock: 60MHz */ 44 #define RO_CLK 60000000 45 46 #define ACCR_D0CS (1 << 26) 47 #define ACCR_PCCE (1 << 11) 48 49 #define PECR_IE(n) ((1 << ((n) * 2)) << 28) 50 #define PECR_IS(n) ((1 << ((n) * 2)) << 29) 51 52 /* crystal frequency to static memory controller multiplier (SMCFS) */ 53 static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; 54 55 /* crystal frequency to HSIO bus frequency multiplier (HSS) */ 56 static unsigned char hss_mult[4] = { 8, 12, 16, 24 }; 57 58 /* 59 * Get the clock frequency as reflected by CCSR and the turbo flag. 60 * We assume these values have been applied via a fcs. 61 * If info is not 0 we also display the current settings. 62 */ 63 unsigned int pxa3xx_get_clk_frequency_khz(int info) 64 { 65 unsigned long acsr, xclkcfg; 66 unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS; 67 68 /* Read XCLKCFG register turbo bit */ 69 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); 70 t = xclkcfg & 0x1; 71 72 acsr = ACSR; 73 74 xl = acsr & 0x1f; 75 xn = (acsr >> 8) & 0x7; 76 hss = (acsr >> 14) & 0x3; 77 78 XL = xl * BASE_CLK; 79 XN = xn * XL; 80 81 ro = acsr & ACCR_D0CS; 82 83 CLK = (ro) ? RO_CLK : ((t) ? XN : XL); 84 HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK; 85 86 if (info) { 87 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n", 88 RO_CLK / 1000000, (RO_CLK % 1000000) / 10000, 89 (ro) ? "" : "in"); 90 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n", 91 XL / 1000000, (XL % 1000000) / 10000, xl); 92 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n", 93 XN / 1000000, (XN % 1000000) / 10000, xn, 94 (t) ? "" : "in"); 95 pr_info("HSIO bus clock: %d.%02dMHz\n", 96 HSS / 1000000, (HSS % 1000000) / 10000); 97 } 98 99 return CLK / 1000; 100 } 101 102 void pxa3xx_clear_reset_status(unsigned int mask) 103 { 104 /* RESET_STATUS_* has a 1:1 mapping with ARSR */ 105 ARSR = mask; 106 } 107 108 /* 109 * Return the current AC97 clock frequency. 110 */ 111 static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk) 112 { 113 unsigned long rate = 312000000; 114 unsigned long ac97_div; 115 116 ac97_div = AC97_DIV; 117 118 /* This may loose precision for some rates but won't for the 119 * standard 24.576MHz. 120 */ 121 rate /= (ac97_div >> 12) & 0x7fff; 122 rate *= (ac97_div & 0xfff); 123 124 return rate; 125 } 126 127 /* 128 * Return the current HSIO bus clock frequency 129 */ 130 static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) 131 { 132 unsigned long acsr; 133 unsigned int hss, hsio_clk; 134 135 acsr = ACSR; 136 137 hss = (acsr >> 14) & 0x3; 138 hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK; 139 140 return hsio_clk; 141 } 142 143 void clk_pxa3xx_cken_enable(struct clk *clk) 144 { 145 unsigned long mask = 1ul << (clk->cken & 0x1f); 146 147 if (clk->cken < 32) 148 CKENA |= mask; 149 else 150 CKENB |= mask; 151 } 152 153 void clk_pxa3xx_cken_disable(struct clk *clk) 154 { 155 unsigned long mask = 1ul << (clk->cken & 0x1f); 156 157 if (clk->cken < 32) 158 CKENA &= ~mask; 159 else 160 CKENB &= ~mask; 161 } 162 163 const struct clkops clk_pxa3xx_cken_ops = { 164 .enable = clk_pxa3xx_cken_enable, 165 .disable = clk_pxa3xx_cken_disable, 166 }; 167 168 static const struct clkops clk_pxa3xx_hsio_ops = { 169 .enable = clk_pxa3xx_cken_enable, 170 .disable = clk_pxa3xx_cken_disable, 171 .getrate = clk_pxa3xx_hsio_getrate, 172 }; 173 174 static const struct clkops clk_pxa3xx_ac97_ops = { 175 .enable = clk_pxa3xx_cken_enable, 176 .disable = clk_pxa3xx_cken_disable, 177 .getrate = clk_pxa3xx_ac97_getrate, 178 }; 179 180 static void clk_pout_enable(struct clk *clk) 181 { 182 OSCC |= OSCC_PEN; 183 } 184 185 static void clk_pout_disable(struct clk *clk) 186 { 187 OSCC &= ~OSCC_PEN; 188 } 189 190 static const struct clkops clk_pout_ops = { 191 .enable = clk_pout_enable, 192 .disable = clk_pout_disable, 193 }; 194 195 static void clk_dummy_enable(struct clk *clk) 196 { 197 } 198 199 static void clk_dummy_disable(struct clk *clk) 200 { 201 } 202 203 static const struct clkops clk_dummy_ops = { 204 .enable = clk_dummy_enable, 205 .disable = clk_dummy_disable, 206 }; 207 208 static struct clk clk_pxa3xx_pout = { 209 .ops = &clk_pout_ops, 210 .rate = 13000000, 211 .delay = 70, 212 }; 213 214 static struct clk clk_dummy = { 215 .ops = &clk_dummy_ops, 216 }; 217 218 static DEFINE_PXA3_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops); 219 static DEFINE_PXA3_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops); 220 static DEFINE_PXA3_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops); 221 static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); 222 static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); 223 static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); 224 static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0); 225 static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5); 226 static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0); 227 static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0); 228 static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0); 229 static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0); 230 static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0); 231 static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0); 232 static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0); 233 static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0); 234 static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0); 235 static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0); 236 static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0); 237 238 static struct clk_lookup pxa3xx_clkregs[] = { 239 INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), 240 /* Power I2C clock is always on */ 241 INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL), 242 INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL), 243 INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"), 244 INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"), 245 INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL), 246 INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL), 247 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL), 248 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"), 249 INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL), 250 INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL), 251 INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL), 252 INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL), 253 INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL), 254 INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL), 255 INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL), 256 INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL), 257 INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL), 258 INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL), 259 INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL), 260 INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL), 261 INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL), 262 }; 263 264 #ifdef CONFIG_PM 265 266 #define ISRAM_START 0x5c000000 267 #define ISRAM_SIZE SZ_256K 268 269 static void __iomem *sram; 270 static unsigned long wakeup_src; 271 272 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 273 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 274 275 enum { SLEEP_SAVE_CKENA, 276 SLEEP_SAVE_CKENB, 277 SLEEP_SAVE_ACCR, 278 279 SLEEP_SAVE_COUNT, 280 }; 281 282 static void pxa3xx_cpu_pm_save(unsigned long *sleep_save) 283 { 284 SAVE(CKENA); 285 SAVE(CKENB); 286 SAVE(ACCR); 287 } 288 289 static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save) 290 { 291 RESTORE(ACCR); 292 RESTORE(CKENA); 293 RESTORE(CKENB); 294 } 295 296 /* 297 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic 298 * memory controller has to be reinitialised, so we place some code 299 * in the SRAM to perform this function. 300 * 301 * We disable FIQs across the standby - otherwise, we might receive a 302 * FIQ while the SDRAM is unavailable. 303 */ 304 static void pxa3xx_cpu_standby(unsigned int pwrmode) 305 { 306 extern const char pm_enter_standby_start[], pm_enter_standby_end[]; 307 void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); 308 309 memcpy_toio(sram + 0x8000, pm_enter_standby_start, 310 pm_enter_standby_end - pm_enter_standby_start); 311 312 AD2D0SR = ~0; 313 AD2D1SR = ~0; 314 AD2D0ER = wakeup_src; 315 AD2D1ER = 0; 316 ASCR = ASCR; 317 ARSR = ARSR; 318 319 local_fiq_disable(); 320 fn(pwrmode); 321 local_fiq_enable(); 322 323 AD2D0ER = 0; 324 AD2D1ER = 0; 325 } 326 327 /* 328 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with 329 * PXA3xx development kits assumes that the resuming process continues 330 * with the address stored within the first 4 bytes of SDRAM. The PSPR 331 * register is used privately by BootROM and OBM, and _must_ be set to 332 * 0x5c014000 for the moment. 333 */ 334 static void pxa3xx_cpu_pm_suspend(void) 335 { 336 volatile unsigned long *p = (volatile void *)0xc0000000; 337 unsigned long saved_data = *p; 338 339 extern void pxa3xx_cpu_suspend(void); 340 extern void pxa3xx_cpu_resume(void); 341 342 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ 343 CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); 344 CKENB |= 1 << (CKEN_HSIO2 & 0x1f); 345 346 /* clear and setup wakeup source */ 347 AD3SR = ~0; 348 AD3ER = wakeup_src; 349 ASCR = ASCR; 350 ARSR = ARSR; 351 352 PCFR |= (1u << 13); /* L1_DIS */ 353 PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ 354 355 PSPR = 0x5c014000; 356 357 /* overwrite with the resume address */ 358 *p = virt_to_phys(pxa3xx_cpu_resume); 359 360 pxa3xx_cpu_suspend(); 361 362 *p = saved_data; 363 364 AD3ER = 0; 365 } 366 367 static void pxa3xx_cpu_pm_enter(suspend_state_t state) 368 { 369 /* 370 * Don't sleep if no wakeup sources are defined 371 */ 372 if (wakeup_src == 0) { 373 printk(KERN_ERR "Not suspending: no wakeup sources\n"); 374 return; 375 } 376 377 switch (state) { 378 case PM_SUSPEND_STANDBY: 379 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); 380 break; 381 382 case PM_SUSPEND_MEM: 383 pxa3xx_cpu_pm_suspend(); 384 break; 385 } 386 } 387 388 static int pxa3xx_cpu_pm_valid(suspend_state_t state) 389 { 390 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 391 } 392 393 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { 394 .save_count = SLEEP_SAVE_COUNT, 395 .save = pxa3xx_cpu_pm_save, 396 .restore = pxa3xx_cpu_pm_restore, 397 .valid = pxa3xx_cpu_pm_valid, 398 .enter = pxa3xx_cpu_pm_enter, 399 }; 400 401 static void __init pxa3xx_init_pm(void) 402 { 403 sram = ioremap(ISRAM_START, ISRAM_SIZE); 404 if (!sram) { 405 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); 406 return; 407 } 408 409 /* 410 * Since we copy wakeup code into the SRAM, we need to ensure 411 * that it is preserved over the low power modes. Note: bit 8 412 * is undocumented in the developer manual, but must be set. 413 */ 414 AD1R |= ADXR_L2 | ADXR_R0; 415 AD2R |= ADXR_L2 | ADXR_R0; 416 AD3R |= ADXR_L2 | ADXR_R0; 417 418 /* 419 * Clear the resume enable registers. 420 */ 421 AD1D0ER = 0; 422 AD2D0ER = 0; 423 AD2D1ER = 0; 424 AD3ER = 0; 425 426 pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; 427 } 428 429 static int pxa3xx_set_wake(unsigned int irq, unsigned int on) 430 { 431 unsigned long flags, mask = 0; 432 433 switch (irq) { 434 case IRQ_SSP3: 435 mask = ADXER_MFP_WSSP3; 436 break; 437 case IRQ_MSL: 438 mask = ADXER_WMSL0; 439 break; 440 case IRQ_USBH2: 441 case IRQ_USBH1: 442 mask = ADXER_WUSBH; 443 break; 444 case IRQ_KEYPAD: 445 mask = ADXER_WKP; 446 break; 447 case IRQ_AC97: 448 mask = ADXER_MFP_WAC97; 449 break; 450 case IRQ_USIM: 451 mask = ADXER_WUSIM0; 452 break; 453 case IRQ_SSP2: 454 mask = ADXER_MFP_WSSP2; 455 break; 456 case IRQ_I2C: 457 mask = ADXER_MFP_WI2C; 458 break; 459 case IRQ_STUART: 460 mask = ADXER_MFP_WUART3; 461 break; 462 case IRQ_BTUART: 463 mask = ADXER_MFP_WUART2; 464 break; 465 case IRQ_FFUART: 466 mask = ADXER_MFP_WUART1; 467 break; 468 case IRQ_MMC: 469 mask = ADXER_MFP_WMMC1; 470 break; 471 case IRQ_SSP: 472 mask = ADXER_MFP_WSSP1; 473 break; 474 case IRQ_RTCAlrm: 475 mask = ADXER_WRTC; 476 break; 477 case IRQ_SSP4: 478 mask = ADXER_MFP_WSSP4; 479 break; 480 case IRQ_TSI: 481 mask = ADXER_WTSI; 482 break; 483 case IRQ_USIM2: 484 mask = ADXER_WUSIM1; 485 break; 486 case IRQ_MMC2: 487 mask = ADXER_MFP_WMMC2; 488 break; 489 case IRQ_NAND: 490 mask = ADXER_MFP_WFLASH; 491 break; 492 case IRQ_USB2: 493 mask = ADXER_WUSB2; 494 break; 495 case IRQ_WAKEUP0: 496 mask = ADXER_WEXTWAKE0; 497 break; 498 case IRQ_WAKEUP1: 499 mask = ADXER_WEXTWAKE1; 500 break; 501 case IRQ_MMC3: 502 mask = ADXER_MFP_GEN12; 503 break; 504 default: 505 return -EINVAL; 506 } 507 508 local_irq_save(flags); 509 if (on) 510 wakeup_src |= mask; 511 else 512 wakeup_src &= ~mask; 513 local_irq_restore(flags); 514 515 return 0; 516 } 517 #else 518 static inline void pxa3xx_init_pm(void) {} 519 #define pxa3xx_set_wake NULL 520 #endif 521 522 static void pxa_ack_ext_wakeup(unsigned int irq) 523 { 524 PECR |= PECR_IS(irq - IRQ_WAKEUP0); 525 } 526 527 static void pxa_mask_ext_wakeup(unsigned int irq) 528 { 529 ICMR2 &= ~(1 << ((irq - PXA_IRQ(0)) & 0x1f)); 530 PECR &= ~PECR_IE(irq - IRQ_WAKEUP0); 531 } 532 533 static void pxa_unmask_ext_wakeup(unsigned int irq) 534 { 535 ICMR2 |= 1 << ((irq - PXA_IRQ(0)) & 0x1f); 536 PECR |= PECR_IE(irq - IRQ_WAKEUP0); 537 } 538 539 static int pxa_set_ext_wakeup_type(unsigned int irq, unsigned int flow_type) 540 { 541 if (flow_type & IRQ_TYPE_EDGE_RISING) 542 PWER |= 1 << (irq - IRQ_WAKEUP0); 543 544 if (flow_type & IRQ_TYPE_EDGE_FALLING) 545 PWER |= 1 << (irq - IRQ_WAKEUP0 + 2); 546 547 return 0; 548 } 549 550 static struct irq_chip pxa_ext_wakeup_chip = { 551 .name = "WAKEUP", 552 .ack = pxa_ack_ext_wakeup, 553 .mask = pxa_mask_ext_wakeup, 554 .unmask = pxa_unmask_ext_wakeup, 555 .set_type = pxa_set_ext_wakeup_type, 556 }; 557 558 static void __init pxa_init_ext_wakeup_irq(set_wake_t fn) 559 { 560 int irq; 561 562 for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { 563 set_irq_chip(irq, &pxa_ext_wakeup_chip); 564 set_irq_handler(irq, handle_edge_irq); 565 set_irq_flags(irq, IRQF_VALID); 566 } 567 568 pxa_ext_wakeup_chip.set_wake = fn; 569 } 570 571 void __init pxa3xx_init_irq(void) 572 { 573 /* enable CP6 access */ 574 u32 value; 575 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); 576 value |= (1 << 6); 577 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); 578 579 pxa_init_irq(56, pxa3xx_set_wake); 580 pxa_init_ext_wakeup_irq(pxa3xx_set_wake); 581 pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL); 582 } 583 584 static struct map_desc pxa3xx_io_desc[] __initdata = { 585 { /* Mem Ctl */ 586 .virtual = 0xf6000000, 587 .pfn = __phys_to_pfn(0x4a000000), 588 .length = 0x00200000, 589 .type = MT_DEVICE 590 } 591 }; 592 593 void __init pxa3xx_map_io(void) 594 { 595 pxa_map_io(); 596 iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc)); 597 pxa3xx_get_clk_frequency_khz(1); 598 } 599 600 /* 601 * device registration specific to PXA3xx. 602 */ 603 604 void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) 605 { 606 pxa_register_device(&pxa3xx_device_i2c_power, info); 607 } 608 609 static struct platform_device *devices[] __initdata = { 610 &pxa27x_device_udc, 611 &pxa_device_pmu, 612 &pxa_device_i2s, 613 &pxa_device_asoc_ssp1, 614 &pxa_device_asoc_ssp2, 615 &pxa_device_asoc_ssp3, 616 &pxa_device_asoc_ssp4, 617 &pxa_device_asoc_platform, 618 &sa1100_device_rtc, 619 &pxa_device_rtc, 620 &pxa27x_device_ssp1, 621 &pxa27x_device_ssp2, 622 &pxa27x_device_ssp3, 623 &pxa3xx_device_ssp4, 624 &pxa27x_device_pwm0, 625 &pxa27x_device_pwm1, 626 }; 627 628 static struct sys_device pxa3xx_sysdev[] = { 629 { 630 .cls = &pxa_irq_sysclass, 631 }, { 632 .cls = &pxa3xx_mfp_sysclass, 633 }, { 634 .cls = &pxa_gpio_sysclass, 635 }, 636 }; 637 638 static int __init pxa3xx_init(void) 639 { 640 int i, ret = 0; 641 642 if (cpu_is_pxa3xx()) { 643 644 reset_status = ARSR; 645 646 /* 647 * clear RDH bit every time after reset 648 * 649 * Note: the last 3 bits DxS are write-1-to-clear so carefully 650 * preserve them here in case they will be referenced later 651 */ 652 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); 653 654 clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs)); 655 656 if ((ret = pxa_init_dma(IRQ_DMA, 32))) 657 return ret; 658 659 pxa3xx_init_pm(); 660 661 for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) { 662 ret = sysdev_register(&pxa3xx_sysdev[i]); 663 if (ret) 664 pr_err("failed to register sysdev[%d]\n", i); 665 } 666 667 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 668 } 669 670 return ret; 671 } 672 673 postcore_initcall(pxa3xx_init); 674