1 /* 2 * linux/arch/arm/mach-pxa/pxa3xx.c 3 * 4 * code specific to pxa3xx aka Monahans 5 * 6 * Copyright (C) 2006 Marvell International Ltd. 7 * 8 * 2007-09-02: eric miao <eric.miao@marvell.com> 9 * initial version 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/kernel.h> 18 #include <linux/init.h> 19 #include <linux/pm.h> 20 #include <linux/platform_device.h> 21 #include <linux/irq.h> 22 #include <linux/io.h> 23 #include <linux/sysdev.h> 24 25 #include <asm/hardware.h> 26 #include <asm/arch/pxa3xx-regs.h> 27 #include <asm/arch/ohci.h> 28 #include <asm/arch/pm.h> 29 #include <asm/arch/dma.h> 30 #include <asm/arch/ssp.h> 31 32 #include "generic.h" 33 #include "devices.h" 34 #include "clock.h" 35 36 /* Crystal clock: 13MHz */ 37 #define BASE_CLK 13000000 38 39 /* Ring Oscillator Clock: 60MHz */ 40 #define RO_CLK 60000000 41 42 #define ACCR_D0CS (1 << 26) 43 #define ACCR_PCCE (1 << 11) 44 45 /* crystal frequency to static memory controller multiplier (SMCFS) */ 46 static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; 47 48 /* crystal frequency to HSIO bus frequency multiplier (HSS) */ 49 static unsigned char hss_mult[4] = { 8, 12, 16, 0 }; 50 51 /* 52 * Get the clock frequency as reflected by CCSR and the turbo flag. 53 * We assume these values have been applied via a fcs. 54 * If info is not 0 we also display the current settings. 55 */ 56 unsigned int pxa3xx_get_clk_frequency_khz(int info) 57 { 58 unsigned long acsr, xclkcfg; 59 unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS; 60 61 /* Read XCLKCFG register turbo bit */ 62 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); 63 t = xclkcfg & 0x1; 64 65 acsr = ACSR; 66 67 xl = acsr & 0x1f; 68 xn = (acsr >> 8) & 0x7; 69 hss = (acsr >> 14) & 0x3; 70 71 XL = xl * BASE_CLK; 72 XN = xn * XL; 73 74 ro = acsr & ACCR_D0CS; 75 76 CLK = (ro) ? RO_CLK : ((t) ? XN : XL); 77 HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK; 78 79 if (info) { 80 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n", 81 RO_CLK / 1000000, (RO_CLK % 1000000) / 10000, 82 (ro) ? "" : "in"); 83 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n", 84 XL / 1000000, (XL % 1000000) / 10000, xl); 85 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n", 86 XN / 1000000, (XN % 1000000) / 10000, xn, 87 (t) ? "" : "in"); 88 pr_info("HSIO bus clock: %d.%02dMHz\n", 89 HSS / 1000000, (HSS % 1000000) / 10000); 90 } 91 92 return CLK / 1000; 93 } 94 95 /* 96 * Return the current static memory controller clock frequency 97 * in units of 10kHz 98 */ 99 unsigned int pxa3xx_get_memclk_frequency_10khz(void) 100 { 101 unsigned long acsr; 102 unsigned int smcfs, clk = 0; 103 104 acsr = ACSR; 105 106 smcfs = (acsr >> 23) & 0x7; 107 clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK; 108 109 return (clk / 10000); 110 } 111 112 /* 113 * Return the current AC97 clock frequency. 114 */ 115 static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk) 116 { 117 unsigned long rate = 312000000; 118 unsigned long ac97_div; 119 120 ac97_div = AC97_DIV; 121 122 /* This may loose precision for some rates but won't for the 123 * standard 24.576MHz. 124 */ 125 rate /= (ac97_div >> 12) & 0x7fff; 126 rate *= (ac97_div & 0xfff); 127 128 return rate; 129 } 130 131 /* 132 * Return the current HSIO bus clock frequency 133 */ 134 static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) 135 { 136 unsigned long acsr; 137 unsigned int hss, hsio_clk; 138 139 acsr = ACSR; 140 141 hss = (acsr >> 14) & 0x3; 142 hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK; 143 144 return hsio_clk; 145 } 146 147 void clk_pxa3xx_cken_enable(struct clk *clk) 148 { 149 unsigned long mask = 1ul << (clk->cken & 0x1f); 150 151 if (clk->cken < 32) 152 CKENA |= mask; 153 else 154 CKENB |= mask; 155 } 156 157 void clk_pxa3xx_cken_disable(struct clk *clk) 158 { 159 unsigned long mask = 1ul << (clk->cken & 0x1f); 160 161 if (clk->cken < 32) 162 CKENA &= ~mask; 163 else 164 CKENB &= ~mask; 165 } 166 167 const struct clkops clk_pxa3xx_cken_ops = { 168 .enable = clk_pxa3xx_cken_enable, 169 .disable = clk_pxa3xx_cken_disable, 170 }; 171 172 static const struct clkops clk_pxa3xx_hsio_ops = { 173 .enable = clk_pxa3xx_cken_enable, 174 .disable = clk_pxa3xx_cken_disable, 175 .getrate = clk_pxa3xx_hsio_getrate, 176 }; 177 178 static const struct clkops clk_pxa3xx_ac97_ops = { 179 .enable = clk_pxa3xx_cken_enable, 180 .disable = clk_pxa3xx_cken_disable, 181 .getrate = clk_pxa3xx_ac97_getrate, 182 }; 183 184 static void clk_pout_enable(struct clk *clk) 185 { 186 OSCC |= OSCC_PEN; 187 } 188 189 static void clk_pout_disable(struct clk *clk) 190 { 191 OSCC &= ~OSCC_PEN; 192 } 193 194 static const struct clkops clk_pout_ops = { 195 .enable = clk_pout_enable, 196 .disable = clk_pout_disable, 197 }; 198 199 static struct clk pxa3xx_clks[] = { 200 { 201 .name = "CLK_POUT", 202 .ops = &clk_pout_ops, 203 .rate = 13000000, 204 .delay = 70, 205 }, 206 207 PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev), 208 PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL), 209 PXA3xx_CK("AC97CLK", AC97, &clk_pxa3xx_ac97_ops, NULL), 210 211 PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), 212 PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), 213 PXA3xx_CKEN("UARTCLK", STUART, 14857000, 1, NULL), 214 215 PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), 216 PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa27x_device_udc.dev), 217 PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev), 218 PXA3xx_CKEN("KBDCLK", KEYPAD, 32768, 0, &pxa27x_device_keypad.dev), 219 220 PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), 221 PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), 222 PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev), 223 PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev), 224 PXA3xx_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev), 225 PXA3xx_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev), 226 227 PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev), 228 PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev), 229 PXA3xx_CKEN("MMCCLK", MMC3, 19500000, 0, &pxa3xx_device_mci3.dev), 230 }; 231 232 #ifdef CONFIG_PM 233 234 #define ISRAM_START 0x5c000000 235 #define ISRAM_SIZE SZ_256K 236 237 static void __iomem *sram; 238 static unsigned long wakeup_src; 239 240 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 241 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 242 243 enum { SLEEP_SAVE_CKENA, 244 SLEEP_SAVE_CKENB, 245 SLEEP_SAVE_ACCR, 246 247 SLEEP_SAVE_COUNT, 248 }; 249 250 static void pxa3xx_cpu_pm_save(unsigned long *sleep_save) 251 { 252 SAVE(CKENA); 253 SAVE(CKENB); 254 SAVE(ACCR); 255 } 256 257 static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save) 258 { 259 RESTORE(ACCR); 260 RESTORE(CKENA); 261 RESTORE(CKENB); 262 } 263 264 /* 265 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic 266 * memory controller has to be reinitialised, so we place some code 267 * in the SRAM to perform this function. 268 * 269 * We disable FIQs across the standby - otherwise, we might receive a 270 * FIQ while the SDRAM is unavailable. 271 */ 272 static void pxa3xx_cpu_standby(unsigned int pwrmode) 273 { 274 extern const char pm_enter_standby_start[], pm_enter_standby_end[]; 275 void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); 276 277 memcpy_toio(sram + 0x8000, pm_enter_standby_start, 278 pm_enter_standby_end - pm_enter_standby_start); 279 280 AD2D0SR = ~0; 281 AD2D1SR = ~0; 282 AD2D0ER = wakeup_src; 283 AD2D1ER = 0; 284 ASCR = ASCR; 285 ARSR = ARSR; 286 287 local_fiq_disable(); 288 fn(pwrmode); 289 local_fiq_enable(); 290 291 AD2D0ER = 0; 292 AD2D1ER = 0; 293 } 294 295 /* 296 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with 297 * PXA3xx development kits assumes that the resuming process continues 298 * with the address stored within the first 4 bytes of SDRAM. The PSPR 299 * register is used privately by BootROM and OBM, and _must_ be set to 300 * 0x5c014000 for the moment. 301 */ 302 static void pxa3xx_cpu_pm_suspend(void) 303 { 304 volatile unsigned long *p = (volatile void *)0xc0000000; 305 unsigned long saved_data = *p; 306 307 extern void pxa3xx_cpu_suspend(void); 308 extern void pxa3xx_cpu_resume(void); 309 310 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ 311 CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); 312 CKENB |= 1 << (CKEN_HSIO2 & 0x1f); 313 314 /* clear and setup wakeup source */ 315 AD3SR = ~0; 316 AD3ER = wakeup_src; 317 ASCR = ASCR; 318 ARSR = ARSR; 319 320 PCFR |= (1u << 13); /* L1_DIS */ 321 PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ 322 323 PSPR = 0x5c014000; 324 325 /* overwrite with the resume address */ 326 *p = virt_to_phys(pxa3xx_cpu_resume); 327 328 pxa3xx_cpu_suspend(); 329 330 *p = saved_data; 331 332 AD3ER = 0; 333 } 334 335 static void pxa3xx_cpu_pm_enter(suspend_state_t state) 336 { 337 /* 338 * Don't sleep if no wakeup sources are defined 339 */ 340 if (wakeup_src == 0) { 341 printk(KERN_ERR "Not suspending: no wakeup sources\n"); 342 return; 343 } 344 345 switch (state) { 346 case PM_SUSPEND_STANDBY: 347 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); 348 break; 349 350 case PM_SUSPEND_MEM: 351 pxa3xx_cpu_pm_suspend(); 352 break; 353 } 354 } 355 356 static int pxa3xx_cpu_pm_valid(suspend_state_t state) 357 { 358 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 359 } 360 361 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { 362 .save_count = SLEEP_SAVE_COUNT, 363 .save = pxa3xx_cpu_pm_save, 364 .restore = pxa3xx_cpu_pm_restore, 365 .valid = pxa3xx_cpu_pm_valid, 366 .enter = pxa3xx_cpu_pm_enter, 367 }; 368 369 static void __init pxa3xx_init_pm(void) 370 { 371 sram = ioremap(ISRAM_START, ISRAM_SIZE); 372 if (!sram) { 373 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); 374 return; 375 } 376 377 /* 378 * Since we copy wakeup code into the SRAM, we need to ensure 379 * that it is preserved over the low power modes. Note: bit 8 380 * is undocumented in the developer manual, but must be set. 381 */ 382 AD1R |= ADXR_L2 | ADXR_R0; 383 AD2R |= ADXR_L2 | ADXR_R0; 384 AD3R |= ADXR_L2 | ADXR_R0; 385 386 /* 387 * Clear the resume enable registers. 388 */ 389 AD1D0ER = 0; 390 AD2D0ER = 0; 391 AD2D1ER = 0; 392 AD3ER = 0; 393 394 pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; 395 } 396 397 static int pxa3xx_set_wake(unsigned int irq, unsigned int on) 398 { 399 unsigned long flags, mask = 0; 400 401 switch (irq) { 402 case IRQ_SSP3: 403 mask = ADXER_MFP_WSSP3; 404 break; 405 case IRQ_MSL: 406 mask = ADXER_WMSL0; 407 break; 408 case IRQ_USBH2: 409 case IRQ_USBH1: 410 mask = ADXER_WUSBH; 411 break; 412 case IRQ_KEYPAD: 413 mask = ADXER_WKP; 414 break; 415 case IRQ_AC97: 416 mask = ADXER_MFP_WAC97; 417 break; 418 case IRQ_USIM: 419 mask = ADXER_WUSIM0; 420 break; 421 case IRQ_SSP2: 422 mask = ADXER_MFP_WSSP2; 423 break; 424 case IRQ_I2C: 425 mask = ADXER_MFP_WI2C; 426 break; 427 case IRQ_STUART: 428 mask = ADXER_MFP_WUART3; 429 break; 430 case IRQ_BTUART: 431 mask = ADXER_MFP_WUART2; 432 break; 433 case IRQ_FFUART: 434 mask = ADXER_MFP_WUART1; 435 break; 436 case IRQ_MMC: 437 mask = ADXER_MFP_WMMC1; 438 break; 439 case IRQ_SSP: 440 mask = ADXER_MFP_WSSP1; 441 break; 442 case IRQ_RTCAlrm: 443 mask = ADXER_WRTC; 444 break; 445 case IRQ_SSP4: 446 mask = ADXER_MFP_WSSP4; 447 break; 448 case IRQ_TSI: 449 mask = ADXER_WTSI; 450 break; 451 case IRQ_USIM2: 452 mask = ADXER_WUSIM1; 453 break; 454 case IRQ_MMC2: 455 mask = ADXER_MFP_WMMC2; 456 break; 457 case IRQ_NAND: 458 mask = ADXER_MFP_WFLASH; 459 break; 460 case IRQ_USB2: 461 mask = ADXER_WUSB2; 462 break; 463 case IRQ_WAKEUP0: 464 mask = ADXER_WEXTWAKE0; 465 break; 466 case IRQ_WAKEUP1: 467 mask = ADXER_WEXTWAKE1; 468 break; 469 case IRQ_MMC3: 470 mask = ADXER_MFP_GEN12; 471 break; 472 default: 473 return -EINVAL; 474 } 475 476 local_irq_save(flags); 477 if (on) 478 wakeup_src |= mask; 479 else 480 wakeup_src &= ~mask; 481 local_irq_restore(flags); 482 483 return 0; 484 } 485 #else 486 static inline void pxa3xx_init_pm(void) {} 487 #define pxa3xx_set_wake NULL 488 #endif 489 490 void __init pxa3xx_init_irq(void) 491 { 492 /* enable CP6 access */ 493 u32 value; 494 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); 495 value |= (1 << 6); 496 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); 497 498 pxa_init_irq(56, pxa3xx_set_wake); 499 pxa_init_gpio(128, NULL); 500 } 501 502 /* 503 * device registration specific to PXA3xx. 504 */ 505 506 static struct platform_device *devices[] __initdata = { 507 /* &pxa_device_udc, The UDC driver is PXA25x only */ 508 &pxa_device_ffuart, 509 &pxa_device_btuart, 510 &pxa_device_stuart, 511 &pxa_device_i2s, 512 &pxa_device_rtc, 513 &pxa27x_device_ssp1, 514 &pxa27x_device_ssp2, 515 &pxa27x_device_ssp3, 516 &pxa3xx_device_ssp4, 517 &pxa27x_device_pwm0, 518 &pxa27x_device_pwm1, 519 }; 520 521 static struct sys_device pxa3xx_sysdev[] = { 522 { 523 .cls = &pxa_irq_sysclass, 524 }, { 525 .cls = &pxa3xx_mfp_sysclass, 526 }, { 527 .cls = &pxa_gpio_sysclass, 528 }, 529 }; 530 531 static int __init pxa3xx_init(void) 532 { 533 int i, ret = 0; 534 535 if (cpu_is_pxa3xx()) { 536 /* 537 * clear RDH bit every time after reset 538 * 539 * Note: the last 3 bits DxS are write-1-to-clear so carefully 540 * preserve them here in case they will be referenced later 541 */ 542 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); 543 544 clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks)); 545 546 if ((ret = pxa_init_dma(32))) 547 return ret; 548 549 pxa3xx_init_pm(); 550 551 for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) { 552 ret = sysdev_register(&pxa3xx_sysdev[i]); 553 if (ret) 554 pr_err("failed to register sysdev[%d]\n", i); 555 } 556 557 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 558 } 559 560 return ret; 561 } 562 563 postcore_initcall(pxa3xx_init); 564