1 /* 2 * linux/arch/arm/mach-pxa/pxa3xx.c 3 * 4 * code specific to pxa3xx aka Monahans 5 * 6 * Copyright (C) 2006 Marvell International Ltd. 7 * 8 * 2007-09-02: eric miao <eric.miao@marvell.com> 9 * initial version 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/kernel.h> 18 #include <linux/init.h> 19 #include <linux/pm.h> 20 #include <linux/platform_device.h> 21 #include <linux/irq.h> 22 #include <linux/io.h> 23 #include <linux/syscore_ops.h> 24 #include <linux/i2c/pxa-i2c.h> 25 26 #include <asm/mach/map.h> 27 #include <asm/suspend.h> 28 #include <mach/hardware.h> 29 #include <mach/gpio.h> 30 #include <mach/pxa3xx-regs.h> 31 #include <mach/reset.h> 32 #include <mach/ohci.h> 33 #include <mach/pm.h> 34 #include <mach/dma.h> 35 #include <mach/smemc.h> 36 37 #include "generic.h" 38 #include "devices.h" 39 #include "clock.h" 40 41 #define PECR_IE(n) ((1 << ((n) * 2)) << 28) 42 #define PECR_IS(n) ((1 << ((n) * 2)) << 29) 43 44 static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); 45 static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); 46 static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); 47 static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0); 48 static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5); 49 static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0); 50 static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0); 51 static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0); 52 static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0); 53 static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0); 54 static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0); 55 static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0); 56 static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0); 57 static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0); 58 static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0); 59 static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0); 60 61 static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops); 62 static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops); 63 static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops); 64 static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops); 65 static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70); 66 67 static struct clk_lookup pxa3xx_clkregs[] = { 68 INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), 69 /* Power I2C clock is always on */ 70 INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL), 71 INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL), 72 INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"), 73 INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"), 74 INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL), 75 INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL), 76 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL), 77 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"), 78 INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL), 79 INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL), 80 INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL), 81 INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL), 82 INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL), 83 INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL), 84 INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL), 85 INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL), 86 INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL), 87 INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL), 88 INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL), 89 INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL), 90 INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL), 91 INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL), 92 }; 93 94 #ifdef CONFIG_PM 95 96 #define ISRAM_START 0x5c000000 97 #define ISRAM_SIZE SZ_256K 98 99 static void __iomem *sram; 100 static unsigned long wakeup_src; 101 102 /* 103 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic 104 * memory controller has to be reinitialised, so we place some code 105 * in the SRAM to perform this function. 106 * 107 * We disable FIQs across the standby - otherwise, we might receive a 108 * FIQ while the SDRAM is unavailable. 109 */ 110 static void pxa3xx_cpu_standby(unsigned int pwrmode) 111 { 112 extern const char pm_enter_standby_start[], pm_enter_standby_end[]; 113 void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); 114 115 memcpy_toio(sram + 0x8000, pm_enter_standby_start, 116 pm_enter_standby_end - pm_enter_standby_start); 117 118 AD2D0SR = ~0; 119 AD2D1SR = ~0; 120 AD2D0ER = wakeup_src; 121 AD2D1ER = 0; 122 ASCR = ASCR; 123 ARSR = ARSR; 124 125 local_fiq_disable(); 126 fn(pwrmode); 127 local_fiq_enable(); 128 129 AD2D0ER = 0; 130 AD2D1ER = 0; 131 } 132 133 /* 134 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with 135 * PXA3xx development kits assumes that the resuming process continues 136 * with the address stored within the first 4 bytes of SDRAM. The PSPR 137 * register is used privately by BootROM and OBM, and _must_ be set to 138 * 0x5c014000 for the moment. 139 */ 140 static void pxa3xx_cpu_pm_suspend(void) 141 { 142 volatile unsigned long *p = (volatile void *)0xc0000000; 143 unsigned long saved_data = *p; 144 #ifndef CONFIG_IWMMXT 145 u64 acc0; 146 147 asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0)); 148 #endif 149 150 extern int pxa3xx_finish_suspend(unsigned long); 151 152 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ 153 CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); 154 CKENB |= 1 << (CKEN_HSIO2 & 0x1f); 155 156 /* clear and setup wakeup source */ 157 AD3SR = ~0; 158 AD3ER = wakeup_src; 159 ASCR = ASCR; 160 ARSR = ARSR; 161 162 PCFR |= (1u << 13); /* L1_DIS */ 163 PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ 164 165 PSPR = 0x5c014000; 166 167 /* overwrite with the resume address */ 168 *p = virt_to_phys(cpu_resume); 169 170 cpu_suspend(0, pxa3xx_finish_suspend); 171 172 *p = saved_data; 173 174 AD3ER = 0; 175 176 #ifndef CONFIG_IWMMXT 177 asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0)); 178 #endif 179 } 180 181 static void pxa3xx_cpu_pm_enter(suspend_state_t state) 182 { 183 /* 184 * Don't sleep if no wakeup sources are defined 185 */ 186 if (wakeup_src == 0) { 187 printk(KERN_ERR "Not suspending: no wakeup sources\n"); 188 return; 189 } 190 191 switch (state) { 192 case PM_SUSPEND_STANDBY: 193 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); 194 break; 195 196 case PM_SUSPEND_MEM: 197 pxa3xx_cpu_pm_suspend(); 198 break; 199 } 200 } 201 202 static int pxa3xx_cpu_pm_valid(suspend_state_t state) 203 { 204 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 205 } 206 207 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { 208 .valid = pxa3xx_cpu_pm_valid, 209 .enter = pxa3xx_cpu_pm_enter, 210 }; 211 212 static void __init pxa3xx_init_pm(void) 213 { 214 sram = ioremap(ISRAM_START, ISRAM_SIZE); 215 if (!sram) { 216 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); 217 return; 218 } 219 220 /* 221 * Since we copy wakeup code into the SRAM, we need to ensure 222 * that it is preserved over the low power modes. Note: bit 8 223 * is undocumented in the developer manual, but must be set. 224 */ 225 AD1R |= ADXR_L2 | ADXR_R0; 226 AD2R |= ADXR_L2 | ADXR_R0; 227 AD3R |= ADXR_L2 | ADXR_R0; 228 229 /* 230 * Clear the resume enable registers. 231 */ 232 AD1D0ER = 0; 233 AD2D0ER = 0; 234 AD2D1ER = 0; 235 AD3ER = 0; 236 237 pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; 238 } 239 240 static int pxa3xx_set_wake(struct irq_data *d, unsigned int on) 241 { 242 unsigned long flags, mask = 0; 243 244 switch (d->irq) { 245 case IRQ_SSP3: 246 mask = ADXER_MFP_WSSP3; 247 break; 248 case IRQ_MSL: 249 mask = ADXER_WMSL0; 250 break; 251 case IRQ_USBH2: 252 case IRQ_USBH1: 253 mask = ADXER_WUSBH; 254 break; 255 case IRQ_KEYPAD: 256 mask = ADXER_WKP; 257 break; 258 case IRQ_AC97: 259 mask = ADXER_MFP_WAC97; 260 break; 261 case IRQ_USIM: 262 mask = ADXER_WUSIM0; 263 break; 264 case IRQ_SSP2: 265 mask = ADXER_MFP_WSSP2; 266 break; 267 case IRQ_I2C: 268 mask = ADXER_MFP_WI2C; 269 break; 270 case IRQ_STUART: 271 mask = ADXER_MFP_WUART3; 272 break; 273 case IRQ_BTUART: 274 mask = ADXER_MFP_WUART2; 275 break; 276 case IRQ_FFUART: 277 mask = ADXER_MFP_WUART1; 278 break; 279 case IRQ_MMC: 280 mask = ADXER_MFP_WMMC1; 281 break; 282 case IRQ_SSP: 283 mask = ADXER_MFP_WSSP1; 284 break; 285 case IRQ_RTCAlrm: 286 mask = ADXER_WRTC; 287 break; 288 case IRQ_SSP4: 289 mask = ADXER_MFP_WSSP4; 290 break; 291 case IRQ_TSI: 292 mask = ADXER_WTSI; 293 break; 294 case IRQ_USIM2: 295 mask = ADXER_WUSIM1; 296 break; 297 case IRQ_MMC2: 298 mask = ADXER_MFP_WMMC2; 299 break; 300 case IRQ_NAND: 301 mask = ADXER_MFP_WFLASH; 302 break; 303 case IRQ_USB2: 304 mask = ADXER_WUSB2; 305 break; 306 case IRQ_WAKEUP0: 307 mask = ADXER_WEXTWAKE0; 308 break; 309 case IRQ_WAKEUP1: 310 mask = ADXER_WEXTWAKE1; 311 break; 312 case IRQ_MMC3: 313 mask = ADXER_MFP_GEN12; 314 break; 315 default: 316 return -EINVAL; 317 } 318 319 local_irq_save(flags); 320 if (on) 321 wakeup_src |= mask; 322 else 323 wakeup_src &= ~mask; 324 local_irq_restore(flags); 325 326 return 0; 327 } 328 #else 329 static inline void pxa3xx_init_pm(void) {} 330 #define pxa3xx_set_wake NULL 331 #endif 332 333 static void pxa_ack_ext_wakeup(struct irq_data *d) 334 { 335 PECR |= PECR_IS(d->irq - IRQ_WAKEUP0); 336 } 337 338 static void pxa_mask_ext_wakeup(struct irq_data *d) 339 { 340 pxa_mask_irq(d); 341 PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0); 342 } 343 344 static void pxa_unmask_ext_wakeup(struct irq_data *d) 345 { 346 pxa_unmask_irq(d); 347 PECR |= PECR_IE(d->irq - IRQ_WAKEUP0); 348 } 349 350 static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type) 351 { 352 if (flow_type & IRQ_TYPE_EDGE_RISING) 353 PWER |= 1 << (d->irq - IRQ_WAKEUP0); 354 355 if (flow_type & IRQ_TYPE_EDGE_FALLING) 356 PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2); 357 358 return 0; 359 } 360 361 static struct irq_chip pxa_ext_wakeup_chip = { 362 .name = "WAKEUP", 363 .irq_ack = pxa_ack_ext_wakeup, 364 .irq_mask = pxa_mask_ext_wakeup, 365 .irq_unmask = pxa_unmask_ext_wakeup, 366 .irq_set_type = pxa_set_ext_wakeup_type, 367 }; 368 369 static void __init pxa_init_ext_wakeup_irq(set_wake_t fn) 370 { 371 int irq; 372 373 for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { 374 irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip, 375 handle_edge_irq); 376 set_irq_flags(irq, IRQF_VALID); 377 } 378 379 pxa_ext_wakeup_chip.irq_set_wake = fn; 380 } 381 382 void __init pxa3xx_init_irq(void) 383 { 384 /* enable CP6 access */ 385 u32 value; 386 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); 387 value |= (1 << 6); 388 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); 389 390 pxa_init_irq(56, pxa3xx_set_wake); 391 pxa_init_ext_wakeup_irq(pxa3xx_set_wake); 392 pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL); 393 } 394 395 static struct map_desc pxa3xx_io_desc[] __initdata = { 396 { /* Mem Ctl */ 397 .virtual = SMEMC_VIRT, 398 .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE), 399 .length = 0x00200000, 400 .type = MT_DEVICE 401 } 402 }; 403 404 void __init pxa3xx_map_io(void) 405 { 406 pxa_map_io(); 407 iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc)); 408 pxa3xx_get_clk_frequency_khz(1); 409 } 410 411 /* 412 * device registration specific to PXA3xx. 413 */ 414 415 void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) 416 { 417 pxa_register_device(&pxa3xx_device_i2c_power, info); 418 } 419 420 static struct platform_device *devices[] __initdata = { 421 &pxa27x_device_udc, 422 &pxa_device_pmu, 423 &pxa_device_i2s, 424 &pxa_device_asoc_ssp1, 425 &pxa_device_asoc_ssp2, 426 &pxa_device_asoc_ssp3, 427 &pxa_device_asoc_ssp4, 428 &pxa_device_asoc_platform, 429 &sa1100_device_rtc, 430 &pxa_device_rtc, 431 &pxa27x_device_ssp1, 432 &pxa27x_device_ssp2, 433 &pxa27x_device_ssp3, 434 &pxa3xx_device_ssp4, 435 &pxa27x_device_pwm0, 436 &pxa27x_device_pwm1, 437 }; 438 439 static int __init pxa3xx_init(void) 440 { 441 int ret = 0; 442 443 if (cpu_is_pxa3xx()) { 444 445 reset_status = ARSR; 446 447 /* 448 * clear RDH bit every time after reset 449 * 450 * Note: the last 3 bits DxS are write-1-to-clear so carefully 451 * preserve them here in case they will be referenced later 452 */ 453 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); 454 455 clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs)); 456 457 if ((ret = pxa_init_dma(IRQ_DMA, 32))) 458 return ret; 459 460 pxa3xx_init_pm(); 461 462 register_syscore_ops(&pxa_irq_syscore_ops); 463 register_syscore_ops(&pxa3xx_mfp_syscore_ops); 464 register_syscore_ops(&pxa_gpio_syscore_ops); 465 register_syscore_ops(&pxa3xx_clock_syscore_ops); 466 467 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 468 } 469 470 return ret; 471 } 472 473 postcore_initcall(pxa3xx_init); 474